26.5 GHz, Integer N/Fractional-N, PLL Synthesizer Data Sheet ADF41513 FEATURES GENERAL DESCRIPTION 1 GHz to 26.5 GHz bandwidth The ADF41513 is an ultralow noise frequency synthesizer that Ultralow noise PLL can be used to implement local oscillators (LOs) as high as Integer N = 235 dBc/Hz, fractional-N = 231 dBc/Hz 26.5 GHz in the upconversion and downconversion sections of High maximum PFD frequency wireless receivers and transmitters. Integer N = 250 MHz, fractional-N = 125 MHz The ADF41513 is designed on a high performance silicon 25-bit fixed/49-bit variable fractional modulus mode geranium (SiGe), bipolar complementary metal-oxide Single-ended reference input semiconductor (BiCMOS) process, achieving a normalized 3.3 V power supply, 3.3 V charge pump phase noise floor of 235 dBc/Hz. The phase frequency Integrated 1.8 V logic capability detector (PFD) operates up to 250 MHz (integer N mode)/ Phase resync 125 MHz (fractional-N mode) for improved phase noise and Programmable charge pump currents: 16 range spur performance. The variable modulus, - modulator allows Digital lock detect extremely fine resolution when using a 49-bit divide value. The 3-wire serial interface with register readback option ADF41513 can be used as an integer N phase-locked loop Hardware and software power-down mode (PLL), or it can be used as a fractional-N PLL with either a fixed Operating range from 40C to +105C modulus for subhertz frequency resolution or variable modulus APPLICATIONS for subhertz exact frequency resolution. Test equipment and instrumentation A complete PLL is implemented when the synthesizer is used Wireless infrastructure with an external loop filter and voltage controlled oscillator Microwave point to point and multipoint radios (VCO). The 26.5 GHz bandwidth eliminates the need for a Very small aperture terminal (VSAT) radios frequency doubler or divider stage, simplifying system Aerospace and defense architecture and reducing cost. The ADF41513 is packaged in a compact, 24-lead, 4 mm 4 mm LFCSP. FUNCTIONAL BLOCK DIAGRAM V AV AV AV AV AV AV R P DD1 DD1 DD2 DD3 DD4 DD5 SET ADF41513 REFERENCE 5-BIT 2 REF IN R COUNTER DOUBLER 2 + PHASE DIVIDER N CHARGE CP FREQUENCY HIGH-Z PUMP DETECTOR GND LOCK DC1 DETECT DC2 OUTPUT MUXOUT MUX AV DD + RF A IN N COUNTER DLD R DIV RF B IN CE SD OUT 25-BIT FIXED/49-BIT VARIABLE FRACTIONAL INTERPOLATOR TX DATA FRACTION INTEGER MODULUS CLK 32-BIT VALUE 25 VALUE 2 VALUE DATA DATA C REG1 REGISTER 1.8V LE REGULATOR C REG2 GND Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 16805-001ADF41513 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register 2 (R2) Map ................................................................... 18 Applications ....................................................................................... 1 Register 3 (R3) Map ................................................................... 18 General Description ......................................................................... 1 Register 4 (R4) Map ................................................................... 19 Functional Block Diagram .............................................................. 1 Register 5 (R5) Map ................................................................... 19 Revision History ............................................................................... 2 Register 6 (R6) Map ................................................................... 21 Specifications ..................................................................................... 3 Register 7 (R7) Map ................................................................... 23 Timing Characteristics ................................................................ 5 Register 8 (R8) Map ................................................................... 24 Absolute Maximum Ratings ............................................................ 6 Register 9 (R9) Map ................................................................... 24 Thermal Resistance ...................................................................... 6 Register 10 (R10) Map ............................................................... 25 ESD Caution .................................................................................. 6 Register 11 (R11) Map ............................................................... 25 Pin Configuration and Function Description .............................. 7 Register 12 (R12) Map ............................................................... 26 Typical Performance Characteristics ............................................. 9 Register 13 (R13) Map ............................................................... 27 Theory of Operation ...................................................................... 11 Applications information .............................................................. 28 Reference Input ........................................................................... 11 Initialization Sequence .............................................................. 28 RF Input Stage ............................................................................. 11 RF Synthesizer: A Worked Example of 25-Bit Fixed Modulus Mode ............................................................................................ 28 N Divider and R Counter .......................................................... 11 RF Synthesizer: A Worked Example of Variable Modulus R Counter .................................................................................... 12 Mode ............................................................................................ 28 PFD and Charge Pump .............................................................. 12 Modulus ....................................................................................... 28 MUXOUT .................................................................................... 12 Reference Doubler and Reference Divider ............................. 28 Lock Detector .............................................................................. 12 Spur Mechanisms ....................................................................... 29 Readback ...................................................................................... 13 Phase Resync ............................................................................... 29 Input Shift Registers ................................................................... 13 Outline Dimensions ....................................................................... 30 Program Modes .......................................................................... 13 Ordering Guide .......................................................................... 30 Register Maps .................................................................................. 14 Register 0 (R0) Map ................................................................... 17 Register 1 (R1) Map ................................................................... 17 REVISION HISTORY 1/2019Revision 0: Initial Version Rev. 0 Page 2 of 30