Microwave Wideband Synthesizer with Integrated VCO Data Sheet ADF5610 power supplies for the PLL circuitry range from 3.1 V to 3.5 V, FEATURES and the VCO supplies are between 4.75 V and 5.25 V. The RF output frequency range: 57 MHz to 14,600 MHz charge pump supply voltage can be extended up to 3.6 V for RFOUT: 7300 MHz to 14,600 MHz improved frequency band overlap and extended upper PDIV/NDIV: 57 MHz to 14,600 MHz frequency range. Fractional-N synthesizer and Integer N synthesizer modes 24-bit fractional modulus The ADF5610 has an integrated VCO with a fundamental Exact frequency mode for 0 Hz frequency error frequency of 3650 MHz to 7300 MHz. These frequencies are Typical PFD spurious: <105 dBc internally doubled and routed to the RFOUT pin. An additional Integrated rms jitter: <40 fs differential output allows the doubled VCO frequency to be Normalized inband phase noise floor FOM divided by 1, 2, 4, 8, 16, 32, 64, or 128, allowing the user to High current mode: 232 dBc/Hz (integer) and 229 dBc/Hz generate RF output frequencies as low as 57 MHz. A simple (fractional) 3-wire serial port interface (SPI) provides control of all on-chip Normal mode: 229 dBc/Hz (integer) and 226 dBc/Hz registers. To conserve power, this divider block can be disabled (fractional) when not needed through the SPI interface. Likewise, the output Maintains frequency lock over 40C to +85C (lock and leave) power for both the single-ended output and the differential Low phase noise VCO output are programmable via the VCO register settings. The 115 dBc/Hz typical at 100 kHz (7.3 GHz) ADF5610 also contains various power-down modes for the 114 dBc/Hz typical at 100 kHz (10 GHz) VCO circuitry and PLL circuitry. 109 dBc/Hz typical at 100 kHz (14.6 GHz) The integrated phase detector (PD) and delta-sigma (-) RFOUT power: 5 dBm modulator, capable of operating at up to 100 MHz, permit wide Programmable divide by 1, 2, 4, 8, 16, 32, 64, or 128 output loop bandwidths and fast frequency tuning with a typical Programmable output power level spurious level of 100 dBc. Typical power dissipation: 815 mW With phase noise levels from 115 dBc/Hz at 7.3 GHz to Programmable low current and power dissipation: <700 mW 109 dBc/Hz at 14.6 GHz, the ADF5610 is equipped to Fast frequency hopping (autocalibration enabled): <40 s 2 minimize blocker effects, and to improve receiver sensitivity 48-terminal, 7 mm 7 mm LGA package: 49 mm and transmitter spectral purity. The low phase noise floor APPLICATIONS eliminates any contribution to modulator and mixer noise floor Military and defense in transmitter applications. Test equipment The ADF5610 is a PLL with integrated VCO. The device features Clock generation an innovative programmable performance technology that Wireless infrastructure enables the ADF5610 to tailor current consumption and Satellite and very small aperture terminal (VSAT) corresponding noise performance to individual applications by Microwave radio selecting either a low current consumption mode or a high GENERAL DESCRIPTION performance mode for improved phase noise performance. The ADF5610 allows implementation of fractional-N or Integer N Additional features of the ADF5610 include approximately 3 dB phase-locked loop (PLL) frequency synthesizers when used of RFOUT gain control in 1.5 dB steps and 5 dB of control on the with an external loop filter and an external reference source. differential port in approximately 2.5 dB steps. Finally, the - The wideband microwave voltage controlled oscillator (VCO) modulator with exact frequency mode enables users to generate design permits frequency operation from 7300 MHz to output frequencies with 0 Hz frequency error. 14600 MHz at a single radio frequency (RF) output. A series of frequency dividers with a differential frequency output allows operation from 57 MHz to 14600 MHz. Analog and digital Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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ADF5610 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Legacy Mode: Serial Port Read Operation .............................. 36 Applications ....................................................................................... 1 Open Mode: Serial Port Write Operation ............................... 37 General Description ......................................................................... 1 Open Mode: Serial Port Read Operation ................................ 37 Revision History ............................................................................... 2 PLL Register Map ........................................................................... 39 Functional Block Diagram .............................................................. 3 ID Register, Reset Strobe Register, and Open Mode Read Register ........................................................................................ 39 Specif icat ions ..................................................................................... 4 RST Register ................................................................................ 39 Timing Specifications .................................................................. 9 Reference Divider (RDIV) Register ......................................... 39 Absolute Maximum Ratings .......................................................... 10 Frequency Register, Integer Part .............................................. 40 Thermal Resistance .................................................................... 10 Frequency Register, Fractional Part ......................................... 40 ESD Caution ................................................................................ 10 VCO SPI Register ....................................................................... 40 Pin Configuration and Function Descriptions ........................... 11 - Configuration Register ...................................................... 41 Typical Performance Characteristics ........................................... 13 Lock Detect Register .................................................................. 41 Theory of Operation ...................................................................... 16 Analog Enable (EN) Register .................................................... 42 PLL Subsystem Overview .......................................................... 16 Charge Pump Register ............................................................... 43 VCO Subsystem Overview ........................................................ 16 Autocalibration Register ............................................................ 43 SPI Configuration of PLL and VCO Subsystems ................... 17 Phase Detector (PD) Register ................................................... 44 VCO Subsystem .......................................................................... 18 Exact Frequency Mode Register ............................................... 44 PLL Subsystem ............................................................................ 24 General-Purpose, SPI, and Reference Divider Soft Reset and Power-On Reset ................................................ 32 (GPO SPI RDIV) Register ...................................................... 44 Power-Down Mode .................................................................... 32 VCO Tune Register .................................................................... 45 General-Purpose Output (GPO) .............................................. 32 Successive Approximation Register ......................................... 46 Chip Identification ..................................................................... 33 General-Purpose 2 Register ...................................................... 46 Power Supply ............................................................................... 33 Built In Self Test (BIST) Register .............................................. 46 Programmable Performance Technology................................ 33 VCO Subsystem Register Map ...................................................... 47 Loop Filter and Frequency Changes ........................................ 33 VCO Power Control Register ................................................... 47 Mute Mode .................................................................................. 34 VCO Differential Output Divider Register ............................. 48 Serial Port Interface ........................................................................ 35 Applications Information .............................................................. 50 SPI Modes of Operation ............................................................ 35 Evaluation Printed Circuit Board (PCB) ................................ 50 Register 0x00 Modes .................................................................. 35 Evaluation Kit Contents ............................................................ 50 Serial Port Mode Decision After Power-On Reset ................. 35 Outline Dimensions ....................................................................... 51 Serial Port Legacy Mode ............................................................ 35 Ordering Guide .......................................................................... 51 Serial Port Legacy Mode: Single PLL ....................................... 35 Serial Port Open Mode .............................................................. 35 Legacy Mode: Serial Port Write Operation ............................. 36 REVISION HISTORY 2/2019Revision 0: Initial Version Rev. 0 Page 2 of 51