4 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec Data Sheet AD1938 FEATURES GENERAL DESCRIPTION PLL generated or direct master clock The AD1938 is a high performance, single-chip codec that pro- Low EMI design vides four analog-to-digital converters (ADCs) with input and 108 dB DAC/107 dB ADC dynamic range and SNR eight digital-to-analog converters (DACs) with single-ended output 94 dB THD + N using the Analog Devices, Inc., patented multibit sigma-delta (-) 3.3 V single supply architecture. An SPI port is included, allowing a microcontroller Tolerance for 5 V logic inputs to adjust volume and many other parameters. Supports 24 bits and 8 kHz to 192 kHz sample rates The AD1938 operates from 3.3 V digital and analog supplies. Differential ADC input The AD1938 is available in a 48-lead (single-ended output) Single-ended DAC output LQFP package. Other members of this family include a diffe- Log volume control with autoramp function 2 rential DAC output and I C control port version. SPI controllable for flexibility The AD1938 is designed for low EMI. This consideration is Software-controllable clickless mute apparent in both the system and circuit design architectures. Software power-down 2 By using the on-board PLL to derive the master clock from Right-justified, left-justified, I S-justified, and TDM modes the LR clock or from an external crystal, the AD1938 elimi- Master and slave modes up to 16-channel input/output nates the need for a separate high frequency master clock and 48-lead LQFP package can also be used with a suppressed bit clock. The DACs and Qualified for automotive applications ADCs are designed using the latest Analog Devices continuous time architectures to further minimize EMI. By using 3.3 V APPLICATIONS supplies, power consumption is minimized, further reducing Automotive audio systems emissions. Home Theater Systems Set-top boxes Digital audio effects processors FUNCTIONAL BLOCK DIAGRAM DIGITAL AUDIO INPUT/OUTPUT AD1938 SERIAL DATA PORT DAC DAC SDATA SDATA ADC DAC OUT IN DIGITAL ADC ANALOG CLOCKS FILTER DAC ANALOG DIGITAL AUDIO AND AUDIO FILTER INPUTS VOLUME OUTPUTS DAC ADC CONTROL TIMING MANAGEMENT AND CONTROL DAC ADC (CLOCK AND PLL) DAC DAC SPI CONTROL PORT PRECISION VOLTAGE REFERENCE CONTROL DATA INPUT/OUTPUT Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20062013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com 05582-001AD1938 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog-to-Digital Converters (ADCs) .................................... 13 Applications ....................................................................................... 1 Digital-to-Analog Converters (DACs) .................................... 13 General Description ......................................................................... 1 Clock Signals ............................................................................... 13 Functional Block Diagram .............................................................. 1 Reset and Power-Down ............................................................. 14 Revision History ............................................................................... 2 Serial Control Port ..................................................................... 14 Specifications ..................................................................................... 3 Power Supply and Voltage Reference ....................................... 15 Test Conditions ............................................................................. 3 Serial Data PortsData Format ............................................... 15 Analog Performance Specifications ........................................... 3 Time-Division Multiplexed (TDM) Modes ............................ 15 Crystal Oscillator Specifications................................................. 4 Daisy-Chain Mode ..................................................................... 19 Digital Input/Output Specifications........................................... 5 Control Registers ............................................................................ 24 Power Supply Specifications........................................................ 5 Definitions ................................................................................... 24 Digital Filters ................................................................................. 6 PLL and Clock Control Registers ............................................. 24 Timing Specifications .................................................................. 7 DAC Control Registers .............................................................. 25 Absolute Maximum Ratings ............................................................ 8 ADC Control Registers .............................................................. 27 Thermal Resistance ...................................................................... 8 Additional Modes ....................................................................... 29 ESD Caution .................................................................................. 8 Applications Circuits ...................................................................... 30 Pin Configuration and Function Descriptions ............................. 9 Outline Dimensions ....................................................................... 31 Typical Performance Characteristics ........................................... 11 Ordering Guide .......................................................................... 31 Theory of Operation ...................................................................... 13 REVISION HISTORY 7/08Rev. 0 to Rev. A 2/13Rev. D to Rev. E Changes to Table 7 ............................................................................. 7 Change to tCLH Parameter, Table 7 .................................................. 7 Changes to Figure 2 ........................................................................... 9 Changes to Table 10 .......................................................................... 9 7/11Rev. C to Rev. D Changes to Clock Signals Section ................................................ 13 Changes to Table 10, DSDATAx/ASDATAx Pin Descriptions ... 9 Changes to Reset and Power-Down Section ............................... 14 Change to Serial Control Port Section ........................................ 14 1/11Rev. B to Rev. C Changes to Table 11 ....................................................................... 14 Added Automotive Information ................................. Throughout Changes to Figure 24 and Figure 25 ............................................ 22 Change to Table 2, Introductory Text ............................................ 4 Changes to Figure 26 ...................................................................... 23 Change to Table 4, Introductory Text ............................................ 5 Changes to Definitions Section .................................................... 24 Change to Table 7, Introductory Text ............................................ 7 Changes to Table 16 ....................................................................... 24 Changes to Ordering Guide .......................................................... 31 Change to Additional Modes Section .......................................... 29 Change to Figure 30 ....................................................................... 30 8/09Rev. A to Rev. B Changes to Table 16 Title............................................................... 24 5/06Revision 0: Initial Version Changes to Figure 18 and Table 19 Titles .................................... 25 Changes to Table 20 Title............................................................... 26 Changes to Table 23 and Table 24 Titles ...................................... 27 Changes to Table 25 Title............................................................... 28 Changes to Ordering Guide .......................................................... 31 Rev. E Page 2 of 32