18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs Data Sheet AD4002/AD4006/AD4010 FEATURES GENERAL DESCRIPTION Easy Drive The AD4002/AD4006/AD4010 are high accuracy, high speed, Greatly reduced input kickback low power, 18-bit, Easy Drive, precision successive approximation Input current reduced to 0.5 A/MSPS register (SAR) analog-to-digital converters (ADCs) that operate Enhanced acquisition phase, 79% of cycle time at 1 MSPS from a single power supply, VDD. The reference voltage, V , is REF First conversion accurate, no latency or pipeline delay applied externally and can be set independent of the supply voltage. Input span compression for single-supply operation The AD4002/AD4006/AD4010 power scales linearly with Fast conversion allows low SPI clock rates throughput. Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface Easy Drive features reduce both signal chain complexity and High performance power consumption while enabling higher channel density. The Pseudo differential analog input range reduced input current, particularly in high-Z mode, coupled with a 0 V to VREF with VREF from 2.4 V to 5.1 V long signal acquisition phase, eliminates the need for a dedicated Throughput: 2 MSPS/1 MSPS/500 kSPS options ADC driver. Easy Drive broadens the range of companion circuitry INL: 3.2 LSB maximum that is capable of driving these ADCs (see Figure 2). Guaranteed 18-bit, no missing codes Input span compression eliminates the need to provide a SNR: 95 dB at fIN = 1 kHz at VREF = 5 V negative supply to the ADC driver amplifier while preserving THD: 125 dB at fIN = 1 kHz, 108 dB at fIN = 100 kHz SINAD: 84.5 dB at fIN = 1 MHz (see Figure 17) access to the full ADC code range. The input overvoltage clamp Oversampled dynamic range protects the ADC inputs against overvoltage events, minimizing 98 dB for OSR = 2 disturbances on the reference pin and eliminating the need for 125 dB for OSR = 1024 external protection diodes. Low power Fast device throughput up to 2 MSPS allows users to accurately Single 1.8 V supply operation with 1.71 V to 5.5 V logic capture high frequency signals and to implement oversampling interface techniques to alleviate the challenges associated with antialias 2.5 mW at 500 kSPS (VDD only) filter designs. Decreased serial peripheral interface (SPI) clock 70 W at 10 kSPS, 14 mW at 2 MSPS (total power) rate requirements reduce digital input/output power consumption, 10-lead packages: 3 mm 3 mm LFCSP, 3 mm 4.90 mm MSOP broadens digital host options, and simplifies the task of sending Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: 40C to +125C data across digital isolation. The SPI-compatible serial user interface is compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic by APPLICATIONS using the separate VIO logic supply. Automated test equipment 25 Machine automation HIGH-Z DISABLED, 2MSPS HIGH-Z ENABLED, 2MSPS 20 Medical equipment Battery-powered equipment 15 Precision data acquisition systems 10 Instrumentation and control systems 5 FUNCTIONAL BLOCK DIAGRAM 0 2.4V TO 5.1V 1.8V 10F 5 REF VDD 10 AD4002/ VIO V 1.8V TO 5V REF AD4006/ HIGH-Z TURBO V /2 SDI REF MODE 15 MODE AD4010 IN+ 0 SCK 3-WIRE OR 4-WIRE SERIAL 18-BIT SDO SPI INTERFACE INTERFACE 20 SAR ADC (DAISY CHAIN, CS) IN CNV STATUS SPAN CLAMP BITS COMPRESSION 25 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 GND INPUT DIFFERENTIAL VOLTAGE (V) Figure 1. Figure 2. Input Current vs. Input Differential Voltage Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. 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Technical Support www.analog.com 16233-001 ANALOG INPUT CURRENT (A) 16233-402AD4002/AD4006/AD4010 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 22 Applications ....................................................................................... 1 Ease of Drive Features ............................................................... 23 Functional Block Diagram .............................................................. 1 Voltage Reference Input ............................................................ 24 General Description ......................................................................... 1 Power Supply ............................................................................... 25 Revision History ............................................................................... 2 Digital Interface .......................................................................... 25 Specif ications ..................................................................................... 4 Register Read/Write Functionality........................................... 27 Timing Specifications .................................................................. 7 Status Bits .................................................................................... 29 Absolute Maximum Ratings ............................................................ 9 CS Mode, 3-Wire Turbo Mode ................................................. 30 Thermal Resistance ...................................................................... 9 CS Mode, 3-Wire Without Busy Indicator ............................. 31 ESD Caution .................................................................................. 9 CS Mode, 3-Wire with Busy Indicator .................................... 32 Pin Configurations and Function Descriptions ......................... 10 CS Mode, 4-Wire Turbo Mode ................................................. 33 Typical Performance Characteristics ........................................... 11 CS Mode, 4-Wire Without Busy Indicator ............................. 34 Terminology .................................................................................... 17 CS Mode, 4-Wire with Busy Indicator .................................... 35 Theory of Operation ...................................................................... 18 Daisy-Chain Mode ..................................................................... 36 Circuit Information .................................................................... 18 Layout Guidelines....................................................................... 37 Converter Operation .................................................................. 19 Evaluating the AD4002/AD4006/AD4010 Performance ........ 37 Transfer Functions...................................................................... 19 Outline Dimensions ....................................................................... 38 Applications Information .............................................................. 20 Ordering Guide .......................................................................... 39 Typical Application Diagrams .................................................. 20 Analog Inputs .............................................................................. 21 REVISION HISTORY 2/2021Rev. 0 to Rev. A Changes to Digital Interface Section ........................................... 25 Added Configuration Register Details Section and Serial Clock Changes to Features Section, General Description Section, and Frequency Requirements Section ................................................. 25 Figure 2 .............................................................................................. 1 Changes to Specifications Section and Table 1 ............................. 4 Added Table 12 and Table 13 Renumbered Sequentially ......... 26 Deleted Figure 2 Renumbered Sequentially ................................. 6 Changes to Register Read/Write Functionality Section and Changes to Timing Specifications Section .................................... 7 Figure 47 .......................................................................................... 27 Changes to Figure 48 ...................................................................... 28 Added Note 1 to Table 2 Renumbered Sequentially ................... 7 Changed Status Word Section to Status Bits Section ................. 29 Added Note 1, Table 3 ...................................................................... 8 Changes to Thermal Resistance Section ........................................ 9 Changes to Status Bits Section, Table 15, and Figure 50 ........... 29 Changes to Table 7 .......................................................................... 10 Changes to CS Mode, 3-Wire Turbo Mode Section, Figure 51, Changes to Typical Performance Characteristics Section ......... 11 and Figure 52 Caption ................................................................... 30 Changes to Circuit Information Section and Table 8 ................ 18 Changes to CS Mode, 3-Wire Without Busy Indicator Section, Changes to Typical Application Diagrams Section .................... 20 Figure 53, and Figure 54 Caption ................................................. 31 Changes to Input Overvoltage Clamp Circuit Section .............. 21 Changes to CS Mode, 3-Wire With Busy Indicator Section, Changes to Table 10 and Driver Amplifier Choice Section ...... 22 Figure 55, and Figure 56 ................................................................ 32 Changes to Multiplexed Applications Section, Input Span Changes to CS Mode, 4-Wire Turbo Mode Section, Figure 57, Compression Section, and High-Z Mode Section ..................... 23 and Figure 58 Caption ................................................................... 33 Deleted Table 12 .............................................................................. 24 Changes to CS Mode, 4-Wire Without Busy Indicator Section Changes to Figure 45, Figure 46, Long Acquisition Phase and Figure 60 Caption ................................................................... 34 Section, and Voltage Reference Input Section ............................ 24 Changes to CS Mode, 4-Wire With Busy Indicator Section and Deleted Table 14 .............................................................................. 25 Figure 62 .......................................................................................... 35 Rev. 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