Increment/Decrement a Dual Digital Potentiometer AD5222 FEATURES FUNCTIONAL BLOCK DIAGRAM 128-Position, 2-Channel Potentiometer Replacement V AD5222 10 kV, 50 kV, 100 kV, 1 MV DD A1 Very Low Power: 40 mA Max UP/DOWN DECODE W1 U/D COUNTER 62.7 V Dual Supply Operation or B1 2.7 V to 5.5 V Single Supply Operation Increment/Decrement Count Control POR APPLICATIONS A2 CS DAC Stereo Channel Audio Level Control UP/DOWN MODE SELECT W2 DECODE AND COUNTER Mechanical Potentiometer Replacement DACSEL ENABLE B2 CLK Remote Incremental Adjustment Applications GND Instrumentation: Gain, Offset Adjustment V SS Programmable Voltage-to-Current Conversion Line Impedance Matching GENERAL DESCRIPTION mechanical or push-button switches (or other contact closure The AD5222 provides a dual channel, 128-position, digitally devices). This simple digital interface eliminates the need for controlled variable-resistor (VR) device. This device performs microcontrollers in front panel interface designs. the same electronic adjustment function as a potentiometer or The AD5222 is available in the surface-mount (SO-14) package. variable resistor. These products were optimized for instrument For ultracompact solutions, selected models are available in the and test equipment push-button applications. Choices between thin TSSOP-14 package. All parts are guaranteed to operate bandwidth or power dissipation are available as a result of the over the extended industrial temperature range of 40 C to wide selection of end-to-end terminal resistance values. +85 C. For 3-wire, SPI-compatible interface applications, see The AD5222 contains two fixed resistors with wiper contacts that the AD5203/AD5204/AD5206, AD7376, and AD8400/AD8402/ tap the fixed resistor value at a point determined by a digitally AD8403 products. controlled up/down counter. The resistance between the wiper 5V and either end point of the fixed resistor provides a constant V DD resistance step size that is equal to the end-to-end resistance = 10 kW /128 = divided by the number of positions (e.g., R STEP A1 CS 78 W ). The variable resistor offers a true adjustable value of U/D W1 U/D resistance, between Terminal A and the wiper, or Terminal B B1 and the wiper. The fixed A-to-B terminal resistance of 10 kW , CLK INCREMENT 50 kW , 100 kW , or 1 MW has a nominal temperature coefficient of 35 ppm/ C. A2 The chip select CS, count CLK and U/D direction control inputs DACSEL W2 set the variable resistor position. The MODE determines whether both VRs are incremented together or independently. With MODE B2 MODE at logic zero, both wipers are incremented UP or DOWN GND V SS without changing the relative settings between the wipers. Also, the relative ratio between the wipers is preserved if either wiper Figure 1. Typical Push-Button Control Application reaches the end of the resistor array. In the independent MODE (Logic 1) only the VR determined by the DACSEL pin is changed. DACSEL (Logic 0) changes RDAC 1. These inputs, which con- trol the internal up/down counter, can be easily generated with REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: (V = 3 V 6 10% or 5 V 6 10%, V = 0 V, V = +V , V = 0 V, 408C < T < +858C, DD SS A DD B A AD5222SPECIFICATIONS unless otherwise noted.) 1 Parameter Symbol Condition Min Typ Max Unit DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs) 2 R-DNL R , V = NC 1 1/4 +1 LSB Resistor Differential NL WB A 2 Resistor Nonlinearity R-INL R , V = NC 1 0.4 +1 LSB WB A Nominal Resistor Tolerance DRV = V , Wiper = No Connect, T = 25 C 30 +30 % AB DD A Resistance Temperature Coefficient R /DTV = V , Wiper = No Connect 35 ppm/ C AB AB DD 3 Wiper Resistance R I = V /R, V = 3 V or 5 V 45 100 W W W DD DD Nominal Resistance Match D R/R CH 1 to 2, V = V , T = 25 C0.21% O AB DD A DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs) Resolution N 7 Bits 4 Integral Nonlinearity INL R = 10 kW , 50 kW , or 100 kW 1 1/4 +1 LSB AB INL R = 1 MW 2 1/2 +2 LSB AB 4 Differential Nonlinearity DNL 1 1/4 +1 LSB Voltage Divider Temperature Coefficient D V /D T Code = 40 20 ppm/ C W H Full-Scale Error V Code = 7F 1 0.5 +0 LSB WFSE H Zero-Scale Error V Code = 00 0 0.5 1 LSB WZSE H RESISTOR TERMINALS 5 Voltage Range V V V V A, B, W SS DD 6 Capacitance A, B C f = 1 MHz, Measured to GND, Code = 40 45 pF A, B H 6 WC f = 1 MHz, Measured to GND, Code = 40 60 pF Capacitance W H Common-Mode Leakage I V = V = V 1nA CM A B W DIGITAL INPUTS AND OUTPUTS V = 5 V/3 V 2.4/2.1 V Input Logic High V IH DD Input Logic Low V V = 5 V/3 V 0.8/0.6 V IL DD Input Current I V = 0 V or 5 V 1 m A IL IN 6 Input Capacitance C 5pF IL POWER SUPPLIES V = 0 V 2.7 5.5 V Power Single-Supply Range V DD RANGE SS Power Dual-Supply Range V 2.3 2.7 V DD/SS RANGE Positive Supply Current I V = 5 V or V = 0 V 15 40 m A DD IH IL Negative Supply Current I V = 2.5 V, V = +2.7 V 15 40 m A SS SS DD 7 Power Dissipation P V = 5 V or V = 0 V, V = 5 V 150 400 m W DISS IH IL DD Power Supply Sensitivity PSS 0.002 0.05 %/% 6, 8, 9 DYNAMIC CHARACTERISTICS Bandwidth 3 dB BW 10K R = 10 kW , Code = 40 1000 kHz AB H BW 50K R = 50 kW , Code = 40 180 kHz AB H BW 100K R = 100 kW , Code = 40 78 kHz AB H BW 1M R = 500 kW , Code = 40 7kHz AB H Total Harmonic Distortion THD V = 1 V rms + 2 V dc, V = 2 V dc, f = 1 kHz 0.005 % W A B Settling Time t R = 10 kW , 1 LSB Error Band 2 m s V W S AB Resistor Noise Voltage e R = 5 kW , f = 1 kHz 14 nV Hz N WB WB 6, 10 INTERFACE TIMING CHARACTERISTICS (Applies to All Parts) Input Clock Pulsewidth t , t Clock Level High or Low 30 ns CH CL CS to CLK Setup Time t 20 ns CSS CS Rise to CLK Hold Time t 20 ns CSH U/D to Clock Fall Setup Time t 10 ns UDS U/D to Clock Fall Hold Time t 30 ns UDH DACSEL to Clock Fall Setup Time t 20 ns DSS DACSEL to Clock Fall Hold Time t 30 ns DSH MODE to Clock Fall Setup Time t 20 ns MDS MODE to Clock Fall Hold Time t 40 ns MDH NOTES 1 Typicals represent average readings at 25 C, V = 5 V. DD 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 22 test circuit. 3 Wiper resistance is not measured on the R = 1 MW models. AB 4 INL and DNL are measured at V with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V = V and V = 0 V. DNL W A DD B specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 21 test circuit. 5 Resistor Terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 P is calculated from (I V ). CMOS logic level inputs result in minimum power dissipation. DISS DD DD 8 Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 9 All dynamic characteristics use V = 5 V. DD 10 See timing diagram for location of measured values. All input control voltages are specified with t = t = 2.5 ns (10% to 90% of +3 V) and timed from a voltage level R F of 1.5 V. Switching characteristics are measured using both V = 5 V or V = 3 V. DD DD Specifications subject to change without notice. REV. 0 2