2 Nonvolatile, I C-Compatible 256-Position, Digital Potentiometer Data Sheet AD5259 FEATURES FUNCTIONAL BLOCK DIAGRAMS Nonvolatile memory maintains wiper settings RDAC V DD 256-position A RDAC V RDAC LOGIC EEPROM W Thin LFCSP-10 (3 mm x 3 mm x 0.8 mm) package REGISTER GND B Compact MSOP-10 (3 mm 4.9 mm 1.1mm) package 2 8 DATA I C-compatible interface SCL SDA 2 I C 8 CONTROL V pin provides increased interface flexibility LOGIC SERIAL INTERFACE End-to-end resistance 5 k, 10 k, 50 k, 100 k AD0 COMMAND DECODE LOGIC Resistance tolerance stored in EEPROM (0.1% accuracy) AD1 AD5259 ADDRESS Power-on EEPROM refresh time < 1ms DECODE LOGIC POWER- Software write protect command ON RESET CONTROL LOGIC Address Decode Pin AD0 and Pin AD1 allow 4 packages per bus Figure 1. Block Diagram 100-year typical data retention at 55C V V LOGIC DD Wide operating temperature 40C to +125C 3 V to 5 V single supply A EEPROM SCL RDAC APPLICATIONS 2 REGISTER I C SDA AND SERIAL AD0 INTERFACE LEVEL LCD panel V adjustment COM SHIFTER AD1 W LCD panel brightness and contrast control COMMAND DECODE LOGIC Mechanical potentiometer replacement in new designs ADDRESS DECODE LOGIC Programmable power supplies CONTROL RF amplifier biasing LOGIC GND B Automotive electronics adjustment Gain control and offset adjustment Figure 2. Block Diagram Showing Level Shifters Fiber to the home systems Electronics level settings CONNECTION DIAGRAM GENERAL DESCRIPTION W 1 10 A The AD5259 provides a compact, nonvolatile LFCSP-10 AD0 2 9 B AD5259 (3 mm 3 mm) or MSOP-10 (3 mm 4.9 mm) packaged AD1 3 8 V TOP VIEW DD (Not to Scale) SDA 4 7 GND solution for 256-position adjustment applications. These SCL 5 6 V LOGIC devices perform the same electronic adjustment function 1 as mechanical potentiometers or variable resistors, but Figure 3. Pinout with enhanced resolution and solid-state reliability. 2 The wiper settings are controllable through an I C-compatible digital interface that is also used to read back the wiper register and EEPROM content. Resistor tolerance is also stored within EEPROM, providing an end-to-end tolerance accuracy of 0.1%. 1 The terms digital potentiometer, VR (variable resistor), and RDAC are used A separate V pin delivers increased interface flexibility. For LOGIC interchangeably. users who need multiple parts on one bus, Address Bit AD0 and Address Bit AD1 allow up to four devices on the same bus. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20052012 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 05026-002 05026-001 05026-003AD5259 Data Sheet TABLE OF CONTENTS 2 Specifications ..................................................................................... 3 I C-Compatible Format ................................................................. 16 Electrical Characteristics ............................................................. 3 Generic Interface ........................................................................ 16 Timing Characteristics ................................................................ 5 Write Modes ................................................................................ 16 Absolute Maximum Ratings ............................................................ 6 Read Modes ................................................................................. 17 ESD Caution .................................................................................. 6 Store/Restore Modes .................................................................. 17 Pin Configuration and Function Descriptions ............................. 7 Tolerance Readback Modes ...................................................... 18 Typical Performance Characteristics ............................................. 8 ESD Protection of Digital Pins and Resistor Terminals ........ 19 Test Circuits ..................................................................................... 13 Power-Up Sequence ................................................................... 19 Theory of Operation ...................................................................... 14 Layout and Power Supply Bypassing ....................................... 19 Programming the Variable Resistor ......................................... 14 Multiple Devices on One Bus ................................................... 19 Programming the Potentiometer Divider ............................... 14 Evaluation Board ........................................................................ 19 2 I C-Compatible Interface............................................................... 15 Display Applications ...................................................................... 20 Writing ......................................................................................... 15 Circuitry ...................................................................................... 20 Storing/Restoring ....................................................................... 15 Outline Dimensions ....................................................................... 21 Reading ........................................................................................ 15 Ordering Guide .......................................................................... 22 REVISION HISTORY 10/12Rev. B to Rev. C Changed Maximum Temperature Value from 85C to 125C 7/05Rev. 0 to Rev. A (Throughout) .................................................................................... 1 Added 10-Lead LFCSP ...................................................... Universal Changes to Table 1 ............................................................................ 3 Changes to Features Section and Updated Outline Dimensions ....................................................... 21 General Description Section ............................................................ 1 Changes to Ordering Guide .......................................................... 22 Changes to Table 1 ............................................................................. 3 5/10Rev. A to Rev. B Changes to Table 2 and Added Figure 4 ......................................... 5 Changes to Table 4 ............................................................................. 7 Changes to Figure 5 .......................................................................... 7 Changes to Figure 27 Caption ...................................................... 11 Changes to Storing/Restoring Section ......................................... 15 Changes to Theory of Operation Section.................................... 14 Changes to Table 7 .......................................................................... 16 2 Changes to I C-Compatible Interface Section ............................ 15 Changes to Table 14 ........................................................................ 17 Changes to Table 5 .......................................................................... 16 Updated Outline Dimensions ....................................................... 21 Changes to Multiple Devices on One Bus Section ..................... 19 Updated Figure 49 Caption ........................................................... 21 Changes to Ordering Guide .......................................................... 21 2/05Revision 0: Initial Version Rev. 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