Dual, 10-Bit nanoDAC with 2 ppm/C Reference, SPI Interface Data Sheet AD5313R FEATURES FUNCTIONAL BLOCK DIAGRAM V V DD GND REF Low drift 2.5 V reference: 2 ppm/C typical Tiny package: 3 mm 3 mm, 16-lead LFCSP AD5313R V LOGIC 2.5V Total unadjusted error (TUE): 0.1% of FSR maximum REFERENCE SCLK Offset error: 1.5 mV maximum INPUT DAC STRING Gain error: 0.1% of FSR maximum V A OUT REGISTER REGISTER DAC A SYNC BUFFER High drive capability: 20 mA, 0.5 V from supply rails STRING INPUT DAC User selectable gain of 1 or 2 (GAIN pin) SDIN V B OUT REGISTER REGISTER DAC B BUFFER Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility SDO 50 MHz SPI with readback or daisy chain POWER-ON GAIN = POWER- Low glitch: 0.5 nV-sec DOWN RESET 1/2 LOGIC Low power: 3.3 mW at 3 V LDAC RESET RSTSEL GAIN 2.7 V to 5.5 V power supply Figure 1. 40C to +105C temperature range APPLICATIONS Optical transceivers Base station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5313R, a member of the nanoDAC family, is a low power, Table 1. Related Devices dual, 10-bit buffered voltage output digital-to-analog converter Interface Reference 12-Bit 10-Bit (DAC). The device includes a 2.5 V, 2 ppm/C internal reference SPI Internal AD5687R N/A (enabled by default) and a gain select pin giving a full-scale output 1 External AD5687 AD5313 of 2.5 V (gain = 1) or 5 V (gain = 2). The AD5313R operates 2 1 IC Internal AD5697R AD5338R from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by 1 External N/A AD5338 design, and exhibits less than 0.1% FSR gain error and 1.5 mV 1 offset error performance. The device is available in a 3 mm The AD5313R and the AD5313 are not pin-to-pin or software compatible likewise, the AD5338R and the AD5338 are not pin-to-pin or software compatible. 3 mm LFCSP package and a TSSOP package. The AD5313R also incorporates a power-on reset circuit and PRODUCT HIGHLIGHTS a RSTSEL pin that ensures that the DAC outputs power up to 1. Precision DC Performance. zero scale or midscale and remain there until a valid write occurs. Total unadjusted error: 0.1% of FSR maximum The part contains a per channel power-down feature that reduces Offset error: 1.5 mV maximum the current consumption of the device to 4 A at 3 V while in Gain error: 0.1% of FSR maximum power-down mode. 2. Low Drift 2.5 V On-Chip Reference. The AD5313R employs a versatile serial peripheral interface 2 ppm/C typical temperature coefficient (SPI) that operates at clock rates up to 50 MHz, and the device 5 ppm/C maximum temperature coefficient contains a V pin that is intended for 1.8 V/3 V/5 V logic. 3. Two Package Options. LOGIC 3 mm 3 mm, 16-lead LFCSP 16-lead TSSOP Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. INTERFACE LOGIC 11254-001AD5313R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Write and Update Commands .................................................. 19 Applications ....................................................................................... 1 Daisy-Chain Operation ............................................................. 19 Functional Block Diagram .............................................................. 1 Readback Operation .................................................................. 20 General Description ......................................................................... 1 Power-Down Operation ............................................................ 20 Product Highlights ........................................................................... 1 LDAC Load DAC (Hardware Pin) ........................................... 21 Revision History ............................................................................... 2 LDAC Mask Register ................................................................. 21 Specif icat ions ..................................................................................... 3 Hardware Reset ( ) .......................................................... 22 RESET AC Characteristics ........................................................................ 4 Reset Select Pin (RSTSEL) ........................................................ 22 Timing Characteristics ................................................................ 5 Internal Reference Setup ........................................................... 22 Daisy-Chain and Readback Timing Characteristics ............... 6 Solder Heat Reflow ..................................................................... 22 Absolute Maximum Ratings ............................................................ 8 Long-Term Temperature Drift ................................................. 22 ESD Caution .................................................................................. 8 Thermal Hysteresis .................................................................... 23 Pin Configurations and Function Descriptions ........................... 9 Applications Information .............................................................. 24 Typical Performance Characteristics ........................................... 10 Microprocessor Interfacing ....................................................... 24 Terminology .................................................................................... 15 AD5313R to ADSP-BF531 Interface ....................................... 24 Theory of Operation ...................................................................... 17 AD5313R to SPORT Interface .................................................. 24 Digital-to-Analog Converter (DAC) ....................................... 17 Layout Guidelines....................................................................... 24 Transfer Function ....................................................................... 17 Galvanically Isolated Interface ................................................. 24 DAC Architecture ....................................................................... 17 Outline Dimensions ....................................................................... 25 Serial Interface ............................................................................ 18 Ordering Guide .......................................................................... 25 Standalone Operation ................................................................ 19 REVISION HISTORY 4/2017Rev. A to Rev. B 1/2014Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Change to Table 2 .............................................................................. 3 Changes to VLOGIC Parameter, Table 2 ............................................ 4 Change to Table 7 .............................................................................. 9 Changes to Table 4 ............................................................................ 5 Deleted Figure 10, Renumbered Sequentially ............................ 10 Changes to Table 5 and Figure 4 ..................................................... 6 Deleted Long-Term Temperature Drift Section and Changes to Figure 5 .......................................................................... 7 Figure 45 .......................................................................................... 23 Changes to Table 6 ............................................................................ 8 RESET 2/2013Revision 0: Initial Version Changes to Description, Table 7 ........................................ 9 Changes to Figure 11 ...................................................................... 10 Changes to Figure 16 to Figure 19 ................................................ 11 Changes to Figure 20 to Figure 23 ................................................ 12 Changes to Figure 29 and Figure 30............................................. 13 Changes to Figure 33 and Figure 34............................................. 14 Changes to Table 9 .......................................................................... 18 Changes to Readback Operation Section .................................... 20 RESET Changes to Hardware Reset ( ) Section ............................... 22 Added Long-Term Temperature Drift Section and Figure 45 ..... 22 Changes to Ordering Guide ................................................................ 25 Rev. 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