Quad, 10-Bit nanoDAC with 2 ppm/C Reference, SPI Interface Data Sheet AD5317R FEATURES FUNCTIONAL BLOCK DIAGRAM V GND V DD REF Low drift 2.5 V reference: 2 ppm/C typical Tiny package: 3 mm 3 mm, 16-lead LFCSP AD5317R 2.5V REFERENCE Total unadjusted error (TUE): 0.1% of FSR maximum V LOGIC STRING INPUT DAC V A Offset error: 1.5 mV maximum OUT DAC A REGISTER REGISTER SCLK BUFFER Gain error: 0.1% of FSR maximum INPUT DAC STRING High drive capability: 20 mA, 0.5 V from supply rails V B OUT DAC B REGISTER REGISTER SYNC BUFFER User selectable gain of 1 or 2 (GAIN pin) INPUT DAC STRING Reset to zero scale or midscale (RSTSEL pin) SDIN V C OUT REGISTER REGISTER DAC C BUFFER 1.8 V logic compatibility SDO INPUT DAC STRING 50 MHz SPI with readback or daisy chain V D OUT REGISTER REGISTER DAC D BUFFER Low glitch: 0.5 nV-sec POWER-ON GAIN POWER- Low power: 3.3 mW at 3 V RESET 1/2 DOWN LOGIC 2.7 V to 5.5 V power supply LDAC RESET RSTSEL GAIN 40C to +105C temperature range Figure 1. APPLICATIONS Digital gain and offset adjustment Programmable attenuators Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5317R, a member of the nanoDAC family, is a low Table 1. Related Devices power, quad, 10-bit buffered voltage output DAC. The device Interface Reference 12-Bit 10-Bit includes a 2.5 V, 2 ppm/C internal reference (enabled by SPI Internal AD5684R 1 default) and a gain select pin giving a full-scale output of 2.5 V External AD5684 AD5317 2 (gain = 1) or 5 V (gain = 2). The device operates from a single I C Internal AD5694R AD5316R 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and External AD5694 AD5316 exhibits less than 0.1% FSR gain error and 1.5 mV offset error 1 The AD5317 and AD5317R are not pin-to-pin or software compatible. performance. The device is available in a 3 mm 3 mm LFCSP and a TSSOP package. PRODUCT HIGHLIGHTS The AD5317R also incorporates a power-on reset circuit and a 1. Precision DC Performance. RSTSEL pin that ensures that the DAC outputs power up to Total unadjusted error: 0.1% of FSR maximum zero scale or midscale and remain at that level until a valid write Offset error: 1.5 mV maximum takes place. Each part contains a per-channel power-down Gain error: 0.1% of FSR maximum feature that reduces the current consumption of the device to 2. Low Drift 2.5 V On-Chip Reference. 4 A at 3 V while in power-down mode. 2 ppm/C typical temperature coefficient The AD5317R employs a versatile SPI interface that operates at 5 ppm/C maximum temperature coefficient clock rates up to 50 MHz and contains a VLOGIC pin intended for 3. Two Package Options. 1.8 V/3 V/5 V logic. 3 mm 3 mm, 16-lead LFCSP 16-lead TSSOP Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. INTERFACE LOGIC 10800-001AD5317R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Write and Update Commands .................................................. 21 Applications ....................................................................................... 1 Daisy-Chain Operation ............................................................. 21 Functional Block Diagram .............................................................. 1 Readback Operation .................................................................. 22 General Description ......................................................................... 1 Power-Down Operation ............................................................ 22 Product Highlights ........................................................................... 1 LDAC Load DAC (Hardware Pin) ........................................... 23 Revision History ............................................................................... 2 LDAC Mask Register ................................................................. 23 Specifications ..................................................................................... 3 Hardware Reset ( ) .......................................................... 24 RESET AC Characteristics ........................................................................ 5 Reset Select Pin (RSTSEL) ........................................................ 24 Timing Characteristics ................................................................ 6 Internal Reference Setup ........................................................... 25 Daisy-Chain and Readback Timing Characteristics ............... 7 Solder Heat Reflow ..................................................................... 25 Absolute Maximum Ratings ............................................................ 9 Long-Term Temperature Drift ................................................. 25 ESD Caution .................................................................................. 9 Thermal Hysteresis .................................................................... 25 Pin Configurations and Function Descriptions ......................... 10 Applications Information .............................................................. 26 Typical Performance Characteristics ........................................... 11 Microprocessor Interfacing ....................................................... 26 Terminology .................................................................................... 17 AD5317R to ADSP-BF531 Interface ........................................ 26 Theory of Operation ...................................................................... 19 AD5317R to SPORT Interface .................................................. 26 Digital-to-Analog Converter .................................................... 19 Layout Guidelines....................................................................... 26 Transfer Function ....................................................................... 19 Galvanically Isolated Interface ................................................. 27 DAC Architecture ....................................................................... 19 Outline Dimensions ....................................................................... 28 Serial Interface ............................................................................ 20 Ordering Guide .......................................................................... 28 Standalone Operation ................................................................ 21 REVISION HISTORY 5/2017Rev. A to Rev. B 2/2014Rev. 0 to Rev. A Changes to Table 2 Summary .......................................................... 3 Change to Table 2 .............................................................................. 3 Changes to Table 3 ............................................................................ 5 Change to Table 7 ........................................................................... 10 Changes to Table 4 and Figure 2 ..................................................... 6 Deleted Figure 10, Renumbered Sequentially ............................ 11 Changes to Table 5 and Figure 4 ..................................................... 7 Deleted Long-Term Temperature Drift Section and Changes to Figure 5 .......................................................................... 8 Figure 50 ...................................................................................... 1025 Changes to Table 6 ............................................................................ 9 Changes to V Pin Description and RESET Pin Description, 7/2012Revision 0: Initial Version LOGIC Table 7 .............................................................................................. 10 Changes to Figure 16 to Figure 19 ................................................ 12 Changes to Figure 20 to Figure 24 ................................................ 13 Changes to Figure 30 ...................................................................... 14 Changes to Figure 37 ...................................................................... 15 Changes to Figure 38 ...................................................................... 16 Changes to Table 8 .......................................................................... 20 Changes to Readback Operation Section .................................... 22 Changes to Hardware Reset (RESET) Section ............................ 24 Added Long-Term Temperature Drift Section and Figure 49 Renumbered Sequentially .............................................................. 25 Changes to Ordering Guide .......................................................... 28 Rev. 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