EVAL-AD5363EBZ Analog Devices

8-Channel, 16-/14-Bit, Serial Input, Voltage Output DAC AD5362/AD5363 FEATURES 8-channel DAC in 52-lead LQFP and 56-lead LFCSP packages 2.5 V to 5.5 V digital interface Guaranteed monotonic to 16/14 bits Digital reset (RESET) Nominal output voltage range of 10 V to +10 V Clear function to user-defined SIGGNDx Multiple output voltage spans available Simultaneous update of DAC outputs Thermal shutdown function APPLICATIONS Channel monitoring multiplexer Instrumentation GPIO function Industrial control systems System calibration function allowing user-programmable Level setting in automatic test equipment (ATE) offset and gain Variable optical attenuators (VOA) Channel grouping and addressing features Optical line cards Data error checking feature SPI-compatible serial interface FUNCTIONAL BLOCK DIAGRAM DV V V CC DD SS AGND DGND LDAC TEMP TEMP OUT VREF0 SENSOR n = 16 FOR AD5362 GROUP 0 8 n = 14 FOR AD5363 CONTROL BUFFER 14 14 PEC OFFSET REGISTER OFS0 DAC 0 REGISTER VOUT0 TO 8 A/B SELECT 8 TO MON IN0 VOUT7 REGISTER MUX 2s BUFFER 6 MON IN1 OUTPUT BUFFER VOUT0 nn n X2A REGISTER A/B DAC 0 AND POWER- MUX n n MUX DAC 0 X1 REGISTER MUX REGISTER DOWN CONTROL 2 X2B REGISTER n n M REGISTER VOUT1 MON OUT n n C REGISTER 2 GPIO GPIO REGISTER VOUT2 BIN/2SCOMP n OUTPUT BUFFER n n X2A REGISTER VOUT3 A/B DAC 3 n n MUX AND POWER- DAC 3 X1 REGISTER MUX REGISTER 2 SYNC DOWN CONTROL X2B REGISTER SIGGND0 n n SDI M REGISTER SERIAL n n SCLK INTERFACE C REGISTER VREF1 SDO GROUP 1 BUFFER 14 n OFFSET OFS1 BUSY DAC 1 REGISTER 8 8 TO A/B SELECT MUX 2s BUFFER REGISTER RESET OUTPUT BUFFER VOUT4 n nn X2A REGISTER DAC 4 AND POWER- n n A/B MUX DAC 4 CLR X1 REGISTER REGISTER DOWN CONTROL MUX 2 X2B REGISTER n n M REGISTER STATE VOUT5 MACHINE n n C REGISTER n VOUT6 n n n OUTPUT BUFFER VOUT7 X2A REGISTER A/B DAC 7 n n MUX DAC 7 AND POWER- X1 REGISTER MUX REGISTER 2 DOWN CONTROL X2B REGISTER SIGGND1 AD5362/ n n M REGISTER AD5363 n n C REGISTER Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05762-001AD5362/AD5363 TABLE OF CONTENTS Features .............................................................................................. 1 Reset Function ............................................................................ 20 Applications ....................................................................................... 1 Clear Function ............................................................................ 20 Functional Block Diagram .............................................................. 1 BUSY and LDAC Functions...................................................... 20 Revision History ............................................................................... 2 BIN/2SCOMP Pin ...................................................................... 20 General Description ......................................................................... 3 Temperature Sensor ................................................................... 20 Specif icat ions ..................................................................................... 4 Monitor Function ....................................................................... 21 AC Characteristics ........................................................................ 6 GPIO Pin ..................................................................................... 21 Timing Characteristics ................................................................ 7 Power-Down Mode .................................................................... 21 Absolute Maximum Ratings .......................................................... 10 Thermal Shutdown Function ................................................... 21 ESD Caution ................................................................................ 10 Toggle Mode ................................................................................ 21 Pin Configuration and Function Descriptions ........................... 11 Serial Interface ................................................................................ 22 Typical Performance Characteristics ........................................... 13 SPI Write Mode .......................................................................... 22 Terminology .................................................................................... 15 SPI Readback Mode ................................................................... 22 Theory of Operation ...................................................................... 16 Register Update Rates ................................................................ 22 DAC Architecture ....................................................................... 16 Packet Error Checking ............................................................... 23 Channel Groups .......................................................................... 16 Channel Addressing and Special Modes ................................. 23 A/B Registers and Gain/Offset Adjustment ............................ 17 Special Function Mode .............................................................. 24 Offset DACs ................................................................................ 17 Applications Information .............................................................. 26 Output Amplifier ........................................................................ 18 Power Supply Decoupling ......................................................... 26 Transfer Function ....................................................................... 18 Power Supply Sequencing ......................................................... 26 Reference Selection .................................................................... 18 Interfacing Examples ................................................................. 26 Calibration ................................................................................... 19 Outline Dimensions ....................................................................... 27 Additional Calibration ............................................................... 19 Ordering Guide .......................................................................... 28 REVISION HISTORY 3/08Rev. 0 to Rev. A Added 56-Lead LFCSP VQ .............................................. Universal Changes to Calibration Section .................................................... 19 Changes to Table 2 ............................................................................ 4 BUSY LDAC Changes to Reset Function Section and and Added t23 Parameter ......................................................................... 7 Functions Section ........................................................................... 20 Changes to Figure 4 .......................................................................... 8 Changes to Channel Addressing and Special Modes Section .. 23 Changes to Table 6 .......................................................................... 11 Updated Outline Dimensions ....................................................... 27 Changes to A/B Registers and Gain/Offset Adjustment Changes to Ordering Guide .......................................................... 28 Section .............................................................................................. 17 1/08Revision 0: Initial Version Rev. A Page 2 of 28