EVAL-AD5373EBZ Analog Devices

DV V CC DD 32-Channel, 16-/14-Bit, Serial Input, Voltage Output DAC AD5372/AD5373 FEATURES 2.5 V to 5.5 V JEDEC-compliant digital levels Digital reset (RESET) 32-channel DAC in a 64-lead LQFP and 64-lead LFCSP 1 Clear function to user-defined SIGGNDx AD5372/AD5373 guaranteed monotonic to 16/14 bits Simultaneous update of DAC outputs Maximum output voltage span of 4 VREF (20 V) Nominal output voltage range of 4 V to +8 V APPLICATIONS Multiple, independent output voltage spans available Level setting in automatic test equipment (ATE) System calibration function allowing user-programmable Variable optical attenuators (VOA) offset and gain Optical switches Channel grouping and addressing features Industrial control systems Thermal shutdown function Instrumentation DSP/microcontroller-compatible serial interface SPI serial interface FUNCTIONAL BLOCK DIAGRAM V SS AGND DGND LDAC VREF0 n = 16 FOR AD5372 n CONTROL GROUP 0 n = 14 FOR AD5373 BUFFER REGISTER 14 n OFS0 OFFSET REGISTER DAC 0 8 8 A/B SELECT TO BUFFER REGISTER MUX 2s OUTPUT BUFFER VOUT0 n n n n n X2A REGISTER AND POWER- DAC 0 DAC 0 X1 REGISTER VOUT1 REGISTER DOWN CONTROL X2B REGISTER n n VOUT2 M REGISTER n n VOUT3 C REGISTER VOUT4 VOUT5 VOUT6 OUTPUT BUFFER n n n n n X2A REGISTER VOUT7 DAC 7 AND POWER- SERIAL DAC 7 X1 REGISTER SYNC REGISTER DOWN CONTROL INTERFACE X2B REGISTER SIGGND0 n n SDI M REGISTER n n SCLK C REGISTER VREF1 SDO GROUP 1 BUFFER 14 n BUSY OFFSET OFS1 DAC 1 REGISTER 8 8 A/B SELECT TO RESET BUFFER REGISTER MUX 2s OUTPUT BUFFER VOUT8 CLR n n n X2A REGISTER n n DAC 0 AND POWER- DAC 0 X1 REGISTER REGISTER VOUT9 DOWN CONTROL X2B REGISTER n n STATE VOUT10 M REGISTER MACHINE n n VOUT11 C REGISTER VOUT12 VOUT13 VOUT14 OUTPUT BUFFER n n n n n VOUT15 X2A REGISTER DAC 7 AND POWER- DAC 7 X1 REGISTER REGISTER DOWN CONTROL X2B REGISTER SIGGND1 n n M REGISTER n n C REGISTER VREF1 SUPPLIES VOUT16 GROUP 2 TO GROUP 3 AD5372/ TO GROUP 1 TO GROUP 3 ARE IDENTICAL TO GROUP 1 VOUT31 AD5373 SIGGND2 SIGGND3 Figure 1. 1 Protected by U.S. Patent No. 5,969,657. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20072011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. A/B A/B A/B A/B MUX MUX MUX MUX MUX MUX MUX MUX 2 2 2 2 05815-001AD5372/AD5373 TABLE OF CONTENTS Features .............................................................................................. 1 Reference Selection .................................................................... 17 Applications....................................................................................... 1 Calibration................................................................................... 18 Functional Block Diagram .............................................................. 1 Additional Calibration............................................................... 19 Revision History ............................................................................... 2 Reset Function ............................................................................ 19 General Description ......................................................................... 3 Clear Function ............................................................................ 19 Specifications..................................................................................... 4 BUSY LDAC and Functions...................................................... 19 AC Characteristics........................................................................ 5 Power-Down Mode.................................................................... 20 Timing Characteristics ................................................................ 6 Thermal Shutdown Function ................................................... 20 Absolute Maximum Ratings............................................................ 9 Toggle Mode................................................................................ 20 ESD Caution.................................................................................. 9 Serial Interface ................................................................................ 21 Pin Configurations and Function Descriptions ......................... 10 SPI Write Mode .......................................................................... 21 Typical Performance Characteristics ........................................... 12 SPI Readback Mode ................................................................... 21 Terminology .................................................................................... 14 Register Update Rates ................................................................ 21 Theory of Operation ...................................................................... 15 Channel Addressing and Special Modes................................. 22 DAC Architecture....................................................................... 15 Special Function Mode.............................................................. 23 Channel Groups.......................................................................... 15 Applications Information .............................................................. 24 A/B Registers and Gain/Offset Adjustment............................ 16 Power Supply Decoupling ......................................................... 24 Load DAC.................................................................................... 16 Power Supply Sequencing ......................................................... 24 Offset DACs ................................................................................ 16 Interfacing Examples ................................................................. 24 Output Amplifier........................................................................ 17 Outline Dimensions....................................................................... 25 Transfer Function ....................................................................... 17 Ordering Guide .......................................................................... 26 Changes to Absolute Maximum Ratings Section..........................9 REVISION HISTORY Changes to Pin Configuration and Function Descriptions 7/11Rev. B to Rev. C Section.............................................................................................. 10 Added 64-Lead LFCSP Package........................................Universal Changes to Reset Function Section.............................................. 18 Change to Features Section ............................................................. 1 Change to General Description Section ........................................ 3 Changes to Table 5............................................................................ 9 12/07Rev. 0 to Rev. A Added Figure 7 Renumbered Sequentially ................................ 10 Changes to Table 3.............................................................................6 Changes to Table 6.......................................................................... 10 Changes to AD5373 Transfer Function Section......................... 16 Updated Outline Dimensions ....................................................... 24 Changes to Calibration Section .................................................... 17 Changes to Ordering Guide .......................................................... 25 Changes to Table 8.......................................................................... 18 Changes to Register Update Rates Section.................................. 20 2/08Rev. A to Rev. B Changes to Ordering Guide .......................................................... 25 Added Table 1.................................................................................... 3 Changes to t Parameter ................................................................. 6 10 8/07Revision 0: Initial Version Added t Parameter ......................................................................... 6 23 Changes to Figure 4.......................................................................... 7 Rev. C Page 2 of 28