8-/10-/12-Bit, High Bandwidth Multiplying DACs with Parallel Interface Data Sheet AD5424/AD5433/AD5445 FEATURES GENERAL DESCRIPTION 1 2.5 V to 5.5 V supply operation The AD5424/AD5433/AD5445 are CMOS 8-, 10-, and 12-bit Fast parallel interface (17 ns write cycle) current output digital-to-analog converters (DACs), respectively. Update rate of 20.4 MSPS These devices operate from a 2.5 V to 5.5 V power supply, INL of 1 LSB for 12-bit DAC making them suitable for battery-powered applications and 10 MHz multiplying bandwidth many other applications. These DACs utilize data readback, 10 V reference input allowing the user to read the contents of the DAC register via Extended temperature range: 40C to +125C the DB pins. On power-up, the internal register and latches are 20-lead TSSOP and chip scale (4 mm 4 mm) packages filled with 0s and the DAC outputs are at zero scale. 8-, 10-, and 12-bit current output DACs As a result of manufacturing with a CMOS submicron process, Upgrades to AD7524/AD7533/AD7545 they offer excellent 4-quadrant multiplication characteristics, Pin-compatible 8-, 10-, and 12-bit DACs in chip scale with large signal multiplying bandwidths of up to 10 MHz. Guaranteed monotonic The applied external reference input voltage (VREF) determines the 4-quadrant multiplication full-scale output current. An integrated feedback resistor (RFB) Power-on reset with brownout detection provides temperature tracking and full-scale voltage output Readback function when combined with an external I-to-V precision amplifier. 0.4 A typical power consumption While these devices are upgrades of the AD5424/AD5433/ APPLICATIONS AD5445 in multiplying bandwidth performance, they have a Portable battery-powered applications latched interface and cannot be used in transparent mode. Waveform generators The AD5424 is available in a small, 20-lead LFCSP and a small, Analog processing 16-lead TSSOP, while the AD5433 and AD5445 DACs are available Instrumentation applications in a small, 20-lead LFCSP and a small, 20-lead TSSOP. Programmable amplifiers and attenuators Digitally controlled calibration The EVAL-AD5445SDZ evaluation board is available for Programmable filters and oscillators evaluating DAC performance. For more information, see the Composite video UG-333 evaluation board user guide. Ultrasound 1 Gain, offset, and voltage trimming U.S Patent No. 5,689,257. FUNCTIONAL BLOCK DIAGRAM V V DD REF R FB AD5424/ R AD5433/ I 1 OUT 8-/10-/12-BIT AD5445 R-2R DAC I 2 OUT POWER-ON DAC REGISTER RESET CS INPUT LATCH R/W GND DB0 DB7/DB9/DB11 DATA INPUTS Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20032016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 03160-001AD5424/AD5433/AD5445 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Operation ....................................................................... 18 Applications ....................................................................................... 1 Bipolar Operation....................................................................... 19 General Description ......................................................................... 1 Single-Supply Applications ....................................................... 20 Functional Block Diagram .............................................................. 1 Adding Gain ................................................................................ 21 Revision History ............................................................................... 2 DACs Used as a Divider or Programmable Gain Element ... 21 Specifications ..................................................................................... 3 Reference Selection .................................................................... 22 Timing Characteristics ..................................................................... 5 Amplifier Selection .................................................................... 22 Absolute Maximum Ratings ............................................................ 6 Parallel Interface ......................................................................... 23 ESD Caution .................................................................................. 6 Microprocessor Interfacing ....................................................... 23 Pin Configurations and Function Descriptions ........................... 7 PCB Layout and Power Supply Decoupling ................................ 24 Typical Performance Characteristics ........................................... 10 Outline Dimensions ....................................................................... 25 Terminology ................................................................................ 17 Ordering Guide .......................................................................... 26 Theory of Operation ...................................................................... 18 REVISION HISTORY 1/16Rev. D to Rev. E Added EPAD Note to Table 6 and EPAD Note to Figure 8 .......... 9 Deleted Positive Output Voltage Section and Figure 53 Deleted the Evaluation Board for AD5424/AD5433/AD5445 Renumbered Sequentially .............................................................. 20 Section and Power Supplies for Evaluation Board Section ....... 23 Changes to Adding Gain Section ................................................. 21 Deleted Figure 59 Renumbered Sequentially ............................ 24 Deleted Figure 60 and Figure 61 .................................................. 25 Changed ADSP-21xx-to-AD5424/AD5433/AD5445 Interface Section to ADSP-2191M-to-AD5424/AD5433/AD5445 Changes to Ordering Guide .......................................................... 26 Interface Section and ADSP-BF5xx-to-AD5424/AD5433/ Deleted Figure 62 and Table 12 Renumbered Sequentially ..... 26 AD5445 Interface Section to Blackfin Processor-to-AD5424/ AD5433/AD5445 Interface Section ............................................. 23 8/09Rev. A to Rev. B Changes to Figure 55 and Figure 57 ............................................. 23 Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 26 Changes to Ordering Guide .......................................................... 29 3/05Rev. 0 to Rev. A 4/13Rev. C to Rev. D Changes to Figure 4 and Table 4 ..................................................... 7 Updated Format .................................................................. Universal Changes to Figure 6 and Table 5 ..................................................... 8 Changes to Specifications ................................................................. 4 Changes to Figure 8 and Table 6 ..................................................... 9 Changes to Figure 49 ...................................................................... 17 Updated Outline Dimensions ....................................................... 25 Changes to Figure 50 ...................................................................... 18 Changes to Ordering Guide .......................................................... 26 Changes to Figure 51, Figure 52, and Figure 54 ......................... 19 Added Microprocessor Interfacing Section ................................ 22 12/12Rev. B to Rev. C Added Figure 59 ............................................................................. 24 Changes to General Description Section ...................................... 1 Added Figure 60 ............................................................................. 25 Added Note 2 to Table 1 .................................................................. 4 Added EPAD Note to Table 4 and EPAD Note to Figure 4 ......... 7 10/03Initial Version: Revision 0 Added EPAD Note to Table 5 and EPAD Note to Figure 6 ......... 8 Rev. E Page 2 of 28