Dual, 16-/12-Bit nanoDAC+ with 2 ppm/C Reference, SPI Interface Data Sheet AD5689R/AD5687R FEATURES FUNCTIONAL BLOCK DIAGRAM V V DD GND REF High relative accuracy (INL): 2 LSB maximum at 16 bits Low drift 2.5 V reference: 2 ppm/C typical AD5689R/AD5687R V LOGIC 2.5V REFERENCE Tiny package: 3 mm 3 mm, 16-lead LFCSP SCLK TUE: 0.1% of FSR maximum INPUT DAC STRING V A OUT Offset error: 1.5 mV maximum REGISTER REGISTER DAC A SYNC BUFFER Gain error: 0.1% of FSR maximum STRING INPUT DAC SDIN V B OUT High drive capability: 20 mA, 0.5 V from supply rails DAC B REGISTER REGISTER BUFFER User-selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) SDO 1.8 V logic compatibility POWER-ON GAIN = POWER- RESET 1/2 DOWN 50 MHz SPI with readback or daisy chain LOGIC Low glitch: 0.5 nV-sec LDAC RESET RSTSEL GAIN Robust 4 kV HBM and 1.5 kV FICDM ESD ratings Figure 1. Low power: 3.3 mW at 3 V 2.7 V to 5.5 V power supply 40C to +105C temperature range APPLICATIONS Optical transceivers Base station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5689R/AD5687R members of the nanoDAC+ Table 1. Dual nanoDAC+ Devices family are low power, dual, 16-/12-bit buffered voltage output Interface Reference 16-Bit 12-Bit digital-to-analog converters (DACs). The devices include SPI Internal AD5689R AD5687R a 2.5 V, 2 ppm/C internal reference (enabled by default) External AD5689 AD5687 and a gain select pin giving a full-scale output of 2.5 V 2 I C Internal N/A AD5697R (gain = 1) or 5 V (gain = 2). The devices operate from External N/A N/A a single 2.7 V to 5.5 V supply, are guaranteed monotonic by design, and exhibit less than 0.1% FSR gain error and 1.5 mV offset error performance. Both devices are available PRODUCT HIGHLIGHTS in a 3 mm 3 mm LFCSP and a TSSOP package. 1. High Relative Accuracy (INL). The AD5689R/AD5687R also incorporate a power-on reset AD5689R (16-bit): 2 LSB maximum circuit and a RSTSEL pin that ensure that the DAC outputs AD5687R (12-bit): 1 LSB maximum power up to zero scale or midscale and remain there until 2. Low Drift 2.5 V On-Chip Reference. a valid write takes place. Each part contains a per channel 2 ppm/C typical temperature coefficient power-down feature that reduces the current consumption 5 ppm/C maximum temperature coefficient of the device to 4 A at 3 V while in power-down mode. 3. Two Package Options. The AD5689R/AD5687R use a versatile serial peripheral 3 mm 3 mm, 16-lead LFCSP interface (SPI) that operates at clock rates up to 50 MHz. 16-lead TSSOP and both devices contain a VLOGIC pin that is intended for 1.8 V/3 V/5 V logic. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. 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INTERFACE LOGIC 11256-001AD5689R/AD5687R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Write and Update Commands .................................................. 21 Applications ....................................................................................... 1 Daisy-Chain Operation ............................................................. 21 Functional Block Diagram .............................................................. 1 Readback Operation .................................................................. 22 General Description ......................................................................... 1 Power-Down Operation ............................................................ 22 Product Highlights ........................................................................... 1 LDAC Load DAC (Hardware Pin) ........................................... 23 Revision History ............................................................................... 2 LDAC Mask Register ................................................................. 23 Specifications ..................................................................................... 3 Hardware Reset ( ) .......................................................... 24 RESET AC Characteristics ........................................................................ 5 Reset Select Pin (RSTSEL) ........................................................ 24 Timing Characteristics ................................................................ 6 Internal Reference Setup ........................................................... 24 Daisy-Chain and Readback Timing Characteristics ............... 7 Solder Heat Reflow ..................................................................... 24 Absolute Maximum Ratings ............................................................ 9 Thermal Hysteresis .................................................................... 25 ESD Caution .................................................................................. 9 Applications Information .............................................................. 26 Pin Configurations and Function Descriptions ......................... 10 Microprocessor Interfacing ....................................................... 26 Typical Performance Characteristics ........................................... 11 AD5689R/AD5687R to ADSP-BF531 Interface ...................... 26 Terminology .................................................................................... 17 AD5689R/AD5687R to SPORT Interface ................................ 26 Theory of Operation ...................................................................... 19 Layout Guidelines....................................................................... 26 Digital-to-Analog Converters ................................................... 19 Galvanically Isolated Interface ................................................. 26 Transfer Function ....................................................................... 19 Outline Dimensions ....................................................................... 27 DAC Architecture ....................................................................... 19 Ordering Guide .......................................................................... 28 Serial Interface ............................................................................ 20 Standalone Operation ................................................................ 21 REVISION HISTORY 5/14Rev. 0 to Rev. A Deleted Long-Term Stability/Drift Parameter, Table 1 ............... 4 Deleted Figure 11 Renumbered Sequentially ............................ 11 Deleted Long-Term Temperature Drift Section ......................... 24 2/13Revision 0: Initial Version Rev. A Page 2 of 28