2 Tiny 16-/14-/12-Bit I C nanoDAC+, with 2 LSB INL (16-Bit) and 2 ppm/C Reference Data Sheet AD5693R/AD5692R/AD5691R/AD5693 FEATURES FUNCTIONAL BLOCK DIAGRAM V V V LOGIC REF DD Ultrasmall package: 2 mm 2 mm, 8-lead LFCSP High relative accuracy (INL): 2 LSB maximum at 16 bits POWER-ON AD5693R/ 2.5V AD5693R/AD5692R/AD5691R RESET AD5692R/ REF LDAC AD5691R Low drift, 2.5 V reference: 2 ppm/C typical REF Selectable span output: 2.5 V or 5 V DAC OUTPUT V 16-/14-/12-BIT REGISTER OUT BUFFER DAC AD5693 RESET External reference only Selectable span output: V or 2 V REF REF INPUT POWER-DOWN RESISTOR CONTROL LOGIC CONTROL LOGIC Total unadjusted error (TUE): 0.06% of FSR maximum NETWORK Offset error: 1.5 mV maximum Gain error: 0.05 % of FSR maximum Low glitch: 0.1 nV-sec SDA SCL A0 GND High drive capability: 20 mA Figure 1. MSOP Low power: 1.2 mW at 3.3 V 1 LDAC OR V OR RESET V V LOGIC REF DD 1.8 V V compatible LOGIC Wide operating temperature range: 40C to +105C AD5693R/ 2 POWER-ON 2.5V REF AD5692R/ RESET APPLICATIONS AD5691R/ AD5693 Process controls REF DAC OUTPUT Data acquisition systems V 16-/14-/12-BIT REGISTER OUT BUFFER DAC Digital gain and offset adjustment Programmable voltage sources Optical modules INPUT POWER-DOWN RESISTOR CONTROL LOGIC CONTROL LOGIC NETWORK GENERAL DESCRIPTION The AD5693R/AD5692R/AD5691R/AD5693, members of the nanoDAC+ family, are low power, single-channel, 16-/14-/12-bit SDA SCL A0 GND buffered voltage output DACs. The devices, except the AD5693, 1 NOT ALL PINS AVAILABLE IN ALL 8-LEAD LFCSP MODELS. include an enabled by default internal 2.5 V reference, offering 2 NOT AVAILABLE IN THE AD5693. 2 ppm/C drift. The output span can be programmed to be 0 V to Figure 2. LFCSP V or 0 V to 2 V . All devices operate from a single 2.7 V to REF REF 5.5 V supply and are guaranteed monotonic by design. The Table 1. Related Devices devices are available in a 2.00 mm 2.00 mm, 8-lead LFCSP or Interface Reference 16-Bit 14-Bit 12-Bit a 10-lead MSOP. SPI Internal AD5683R AD5682R AD5681R External AD5683 The internal power-on reset circuit ensures that the DAC register 2 I C Internal AD5693R AD5692R AD5691R is written to zero scale at power-up while the internal output External AD5693 buffer is configured in normal mode. The AD5693R/AD5692R/ AD5691R/AD5693 contain a power-down mode that reduces the PRODUCT HIGHLIGHTS current consumption of the device to 2 A (maximum) at 5 V and provides software selectable output loads. 1. High relative accuracy (INL): 2 LSB maximum 2 (AD5693R/AD5693, 16-bit). The AD5693R/AD5692R/AD5691R/AD5693 use an I C 2. Low drift, 2.5 V on-chip reference: 2 ppm/C typical and interface. Some device options also include an asynchronous 5 ppm/C maximum temperature coefficient. RESET pin and a V pin, allowing 1.8 V compatibility. LOGIC 3. 2 mm 2 mm, 8-lead LFCSP and 10-lead MSOP. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 12077-001 12077-002AD5693R/AD5692R/AD5691R/AD5693 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital-to-Analog Converter .................................................... 19 Applications ....................................................................................... 1 Transfer Function ....................................................................... 19 General Description ......................................................................... 1 DAC Architecture ....................................................................... 19 Functional Block Diagram .............................................................. 1 Serial Interface ................................................................................ 20 2 Product Highlights ........................................................................... 1 I C Serial Data Interface ............................................................ 20 2 Revision History ............................................................................... 2 I C Address .................................................................................. 20 Specif icat ions ..................................................................................... 3 Write Operation.......................................................................... 20 AC Characteristics ........................................................................ 5 Read Operation........................................................................... 22 Timing Characteristics ................................................................ 5 Load DAC (Hardware LDAC Pin) ........................................... 23 Absolute Maximum Ratings ............................................................ 7 Hardware RESET ........................................................................ 23 Thermal Resistance ...................................................................... 7 Thermal Hysteresis .................................................................... 23 ESD Caution .................................................................................. 7 Power-Up Sequence ................................................................... 23 Pin Configurations and Function Descriptions ........................... 8 Recommended Regulator .......................................................... 24 Typical Performance Characteristics ........................................... 12 Layout Guidelines....................................................................... 24 Terminology .................................................................................... 18 Outline Dimensions ....................................................................... 25 Theory of Operation ...................................................................... 19 Ordering Guide .......................................................................... 26 REVISION HISTORY 2/2017Rev. C to Rev. D 5/2014Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Added AD5693 ................................................................... Universal Changes to Specifications Section .................................................. 3 Changes to Features, General Description, Figure 2, Table 1, Changes to VLOGIC Parameter, Table 2 ............................................ 4 and Product Highlights .................................................................... 1 Changes to AC Characteristics Section and Timing Added AD5693 Parameter, Table 1 and AD5693 Parameter, Characteristics Section ..................................................................... 5 Table 1 ................................................................................................. 3 Changes to Table 5 ............................................................................ 7 Changes to Endnote 1, Specifications Section, Table 1 ................ 4 RESET Change to Total Harmonic Distortion, AC Characteristics, Changes to Pin Description, Table 7................................. 8 Table 3 and Endnote 2, Table 3 ........................................................ 5 RESET Changes to Pin Description, Table 10 ............................ 11 Changes to Endnote 7, Timing Characteristics, Table 4 .............. 5 Changes to Figure 49 ...................................................................... 22 Change to Pin 9, Description, Table 7 ............................................ 8 Changes to Figure 6 and Table 8 ...................................................... 9 5/2016Rev. B to Rev. C Change to Figure 11 ....................................................................... 10 Changed VLOGIC = 1.8 V to 5.5 V to VLOGIC = 1.8 V 10% to 5 V + Change to Figure 18 ....................................................................... 11 10% .................................................................................. Throughout Change to the External Reference Section .................................. 17 Changes to Features Section............................................................ 1 Change to Figure 46 ....................................................................... 19 Changes to V Parameter, Table 2 ............................................ 4 LOGIC Change to Figure 48 ....................................................................... 20 Changes to Table 7 ............................................................................ 8 Change to Figure 50 ....................................................................... 21 Changes to Table 9 .......................................................................... 10 Changes to Ordering Guide .......................................................... 23 Changes to Terminology Section.................................................. 18 2/2014Revision 0: Initial Version 11/2014Rev. A to Rev. B Changes to Figure 2 .......................................................................... 1 Changes to Table 8 ............................................................................ 9 Change to Figure 7 ......................................................................... 10 Added Table 9 Renumbered Sequentially .................................. 10 Added Figure 8 Renumbered Sequentially, and Table 10 ......... 11 Added Recommended Regulator Section ................................... 24 Changes to Ordering Guide .......................................................... 26 Rev. D Page 2 of 26