Complete Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC Data Sheet AD5764R FEATURES GENERAL DESCRIPTION Complete quad, 16-bit digital-to-analog converter (DAC) The AD5764R is a quad, 16-bit, serial input, bipolar voltage output Programmable output range: 10 V, 10.2564 V, or 10.5263 V DAC that operates from supply voltages of 11.4 V to 16.5 V. 1 LSB maximum INL error, 1 LSB maximum DNL error Nominal full-scale output range is 10 V. The AD5764R provides Low noise: 60 nV/Hz integrated output amplifiers, reference buffers, and proprietary Settling time: 10 s maximum power-up/power-down control circuitry. The part also features Integrated reference buffers a digital I/O port, programmed via the serial interface, and an Internal reference: 10 ppm/C maximum analog temperature sensor. The part incorporates digital offset On-chip die temperature sensor and gain adjust registers per channel. Output control during power-up/brownout The AD5764R is a high performance converter that provides Programmable short-circuit protection guaranteed monotonicity, integral nonlinearity (INL) of 1 LSB, Simultaneous updating via LDAC low noise, and 10 s settling time. The AD5764R includes an Asynchronous CLR to zero code on-chip 5 V reference with a reference temperature coefficient Digital offset and gain adjust of 10 ppm/C maximum. During power-up when the supply Logic output control pins voltages are changing, VOUTx is clamped to 0 V via a low DSP-/microcontroller-compatible serial interface impedance path. Temperature range: 40C to +85C The AD5764R is based on the iCMOS technology platform, iCMOS process technology which is designed for analog systems designers within industrial/ APPLICATIONS instrumentation equipment OEMs who need high performance ICs at higher voltage levels. iCMOS enables the development of Industrial automation analog ICs capable of 30 V and operation at 15 V supplies, while Open-loop/closed-loop servo control allowing reductions in power consumption and package size, Process control coupled with increased ac and dc performance. Data acquisition systems Automatic test equipment The AD5764R uses a serial interface that operates at clock rates Automotive test and measurement of up to 30 MHz and is compatible with DSP and microcontroller High accuracy instrumentation interface standards. Double buffering allows the simultaneous updating of all DACs. The input coding is programmable to either twos complement or offset binary formats. The asynchronous clear function clears all data registers to either bipolar zero or zero scale, depending on the coding used. The AD5764R is ideal for both closed-loop servo control and open-loop control applications. The AD5764R is available in a 32-lead TQFP and offers guaranteed specifications over the 40C to +85C industrial temperature range (see Figure 1 for the functional block diagram). Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20082011 Analog Devices, Inc. All rights reserved. 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AD5764R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Function Register ....................................................................... 24 Applications ....................................................................................... 1 Data Register ............................................................................... 25 General Description ......................................................................... 1 Coarse Gain Register ................................................................. 25 Revision History ............................................................................... 2 Fine Gain Register ...................................................................... 25 Functional Block Diagram .............................................................. 3 Offset Register ............................................................................ 26 Specifications ..................................................................................... 4 Offset and Gain Adjustment Worked Example ...................... 26 AC Performance Characteristics ................................................ 6 Design Features ............................................................................... 27 Timing Characteristics ................................................................ 7 Analog Output Control ............................................................. 27 Absolute Maximum Ratings .......................................................... 10 Digital Offset and Gain Control ............................................... 27 Thermal Resistance .................................................................... 10 Programmable Short-Circuit Protection ................................ 27 ESD Caution ................................................................................ 10 Digital I/O Port ........................................................................... 27 Pin Configuration and Function Descriptions ........................... 11 Die Temperature Sensor ............................................................ 27 Typical Performance Characteristics ........................................... 13 Local Ground Offset Adjust ...................................................... 27 Terminology .................................................................................... 19 Applications Information .............................................................. 28 Theory of Operation ...................................................................... 21 Typical Operating Circuit ......................................................... 28 DAC Architecture ....................................................................... 21 Layout Guidelines ........................................................................... 30 Reference Buffers ........................................................................ 21 Galvanically Isolated Interface ................................................. 30 Serial Interface ............................................................................ 21 Microprocessor Interfacing ....................................................... 30 Simultaneous Updating via LDAC ........................................... 22 Evaluation Board ........................................................................ 31 Outline Dimensions ....................................................................... 32 Transfer Function ....................................................................... 23 Ordering Guide .......................................................................... 32 CLR Asynchronous Clear ( ) ....................................................... 23 Registers ........................................................................................... 24 REVISION HISTORY 10/11Rev. C to Rev. D 2/09Rev. 0 to Rev. A Changed 50 MHz to 30 MHz ....................................... Throughout Changes to Table 1 Test Conditions/Comments and Changes to t , t , and t Parameters, Table 3 .................................. 7 Added Endnote to Table 1 ................................................................ 4 1 2 3 Added Endnote to Table 2 ................................................................ 6 7/11Rev. B to Rev. C Added Endnote to Table 3 ................................................................ 7 Changed 30 MHz to 50 MHz Throughout.................................... 1 Changes to t1, t2, and t3 Parameters, Table 3 .................................. 7 10/08Revision 0: Initial Version 8/09Rev. A to Rev. B Deleted Endnote 1 in Table 1 .......................................................... 4 Deleted Endnote 1 in Table 2 .......................................................... 6 Deleted Endnote 1 and Changes t6 Parameter in Table 3 ............ 7 Changes to Ordering Guide .......................................................... 32 Rev. D Page 2 of 32