16-Channel, 12-Bit Voltage Output denseDAC Data Sheet AD5767 The AD5767 has integrated output buffers that can sink or FEATURES source up to 20 mA. In conjunction with these buffers, a low Complete 16-channel, 12-bit digital-to-analog converter frequency signal can be superimposed onto each DAC output via 4 mm 4 mm WLCSP package dedicated dither pins. These dedicated dither pins simplify the Integrated DAC output buffers with 20 mA output current system design by reducing the number of external components capability required for a similar external implementation, like operational Integrated reference buffers Channel monitoring multiplexer amplifiers or resistors. The reduction of external components 1.8 V logic compatibility makes the AD5767 suitable for indium phosphide Mach Zehnder Temperature range: 40C to +105C modulator (InP MZM) biasing applications. The device incorporates a power-on reset (POR) circuit that APPLICATIONS ensures that the DAC outputs are clamped to GND on power up Mach Zehnder modulator bias control and remain at this level until the output range of the DAC is Optical modules configured. The outputs of all DACs are updated through Bias control Analog output modules register configuration, with the added functionality of user- selectable DAC channels to be simultaneously updated. GENERAL DESCRIPTION The AD5767 utilizes a versatile 4-wire serial interface that The AD5767 is a 16-channel, 12-bit, voltage output denseDAC operates at clock rates of up to 50 MHz for write mode and is digital-to-analog converter (DAC). compatible with serial peripheral interface (SPI), QSPI, The DAC generates output voltage ranges from an external MICROWIRE, and DSP interface standards. The AD5767 also 2.5 V reference. Depending on the voltage range selected, the contains a VLOGIC pin intended for 1.8 V/3 V/5 V logic. midpoint of the output span can be adjusted, allowing a minimum The AD5767 is available in a 4 mm 4 mm WLCSP package output voltage as low as 20 V or a maximum output voltage of and a 40-lead LFCSP package. The AD5767 operates at a up to +14 V. Each of the 16 channels can be monitored with an temperature range of 40C to +105C. integrated output multiplexer. FUNCTIONAL BLOCK DIAGRAM V AV AV REF CC DD V 0 OUT RANGE 16-TO-1 AD5767 MUX OUT V SET DAC MUX LOGIC V 15 OUT n n INPUT DAC DAC 0 V 0 SDI OUT INPUT REGISTER 0 REGISTER 0 SHIFT SCLK REGISTER AND n SYNC INPUT DAC CONTROL V 1 DAC 1 OUT REGISTER 1 REGISTER 1 LOGIC SDO RESET n INPUT DAC DAC 15 V 15 OUT REGISTER 15 REGISTER 15 DGND AV AGND SS AGND N0 N1 Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 15145-001AD5767 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register Details ............................................................................... 25 Applications ....................................................................................... 1 Input Shift Register .................................................................... 25 General Description ......................................................................... 1 Monitor Mux Control ................................................................ 26 Functional Block Diagram .............................................................. 1 No Operation .............................................................................. 27 Revision History ............................................................................... 2 Daisy-Chain Mode ..................................................................... 27 Specifications ..................................................................................... 3 Write and Update Commands .................................................. 27 AC Performance Characteristics ................................................ 6 Span Register ............................................................................... 28 Timing Characteristics ................................................................ 7 Power Control Register.............................................................. 28 Absolute Maximum Ratings ............................................................ 9 Write Input Data to All DAC Registers ................................... 29 Thermal Resistance ...................................................................... 9 Software Full Reset ..................................................................... 29 ESD Caution .................................................................................. 9 Select Register for Readback ..................................................... 29 Pin Configuration and Function Descriptions ........................... 10 Apply N0 or N1 Dither Signal to DACs Register ................... 30 Typical Performance Characteristics ........................................... 14 Dither Scale ................................................................................. 31 Dither ........................................................................................... 18 Invert Dither Register ................................................................ 31 Terminology .................................................................................... 20 Applications Information .............................................................. 32 Theory of Operation ...................................................................... 22 Dither Configuration ................................................................. 32 Digital-to-Analog Converter .................................................... 22 Thermal Considerations ............................................................ 32 DAC Architecture ....................................................................... 22 Microprocessor Interfacing ....................................................... 32 Resistor String ............................................................................. 22 AD5767 to SPI Interface ............................................................ 32 Power-On Reset (POR) .............................................................. 22 Layout Guidelines....................................................................... 33 Dither ........................................................................................... 23 Outline Dimensions ....................................................................... 34 Power-Down Mode .................................................................... 23 Ordering Guide .......................................................................... 35 Monitor Mux ............................................................................... 23 Serial Interface ............................................................................ 24 REVISION HISTORY 4/2017Rev. 0 to Rev. A Changes to Dither DC Shift Section ............................................ 20 Added 40-Lead LFCSP Package ........................................ Universal Changes to Figure 43, Caption Only............................................ 23 Changes to Input Shift Register Section and Table 9 ................. 25 Changes to Features .......................................................................... 1 Changes to Table 18 ........................................................................ 27 Changes to General Description .................................................... 1 Changes to Functional Block Diagram, Figure 1 ......................... 1 Changes to Thermal Considerations Section ............................. 32 Added Figure 6 and Added Table 7, Renumbered Changes to Layout Guidelines Section and Added Figure 47 .. 33 Sequentially ..................................................................................... 12 Updated Outline Dimensions ....................................................... 34 Changes to Ordering Guide .......................................................... 35 Changes to Figure 23 and Figure 24 ............................................. 16 Added Figure 26 .............................................................................. 17 Changes to Figure 28 and Figure 29 ............................................. 17 1/2017Revision 0: Initial Version Rev. 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