24-Bit, 4-Channel Simultaneous Sampling 1.5 MSPS Precision Alias Free ADC Data Sheet AD7134 FEATURES Sinc3 filter with 50 Hz/60 Hz rejection Crosstalk: 130.7 dBFS Alias free: inherent antialias rejection high performance Daisy-chaining mode 102.5 dB, typical CRC error checking on data and SPI interface Excellent ac and dc performance Two power modes: high performance mode and low power 108 dB dynamic range at ODR = 374 kSPS, FIR filter, typical mode 137 dB dynamic range at ODR = 10 SPS, sinc3 filter, typical Power supply: 4.5 V to 5.5 V and 1.65 V to 1.95 V THD: 120 dB typical with 1 kHz input tone 1.8 V IOVDD level Offset error drift: 0.7 V/C typical External reference: 4.096 V or 5 V Gain drift: 2 ppm/C typical Crystal or external CMOS clock of 48 MHz INL: 2 ppm of FSR typical SPI or pin (standalone) configurable operation Dynamic range enhancement: 4:1 and 2:1 averaging mode Operating temperature range: 0C to 85C 126 dB, A weighted dynamic range Available in 8 mm 8 mm, 56-lead LFCSP with exposed pad Resistive ADC and reference input Easy to sync: asynchronous sample rate converter APPLICATIONS Multidevice synchronization with one signal line Electrical test and measurement Programmable data rates from 0.01 kSPS to 1496 kSPS Audio test with resolution of 0.01 SPS 3-phase power quality analysis Option to control output data rate by external signal Control and hardware in loop verification Linear phase digital filter options Sonars Low ripple FIR filter: 32 dB pass-band ripple, dc to Condition monitoring for predictive maintenance 161.942 kHz Acoustic and material science research and development Low latency sinc3 filter and sinc6 filter, dc to 391.5 kHz FUNCTIONAL BLOCK DIAGRAM FORMAT0/CS MODULATOR CLOCK FORMAT1/SCLK VCM REFERENCE MANAGEMENT 1/2 LDOIN LDO DEC1/DCLKMODE MCLK ODR DEC0/DCLKIO ASYNCHRONOUS AIN0+ CTSD DEC2/SDI PROGRAMMABLE SAMPLE RATE MODULATOR DIGITAL FILTER AIN0 DEC3/SDO CONVERTER DCLK ODR AIN1+ ASYNCHRONOUS CTSD PROGRAMMABLE DIGITAL SAMPLE RATE MODULATOR INTERFACE DIGITAL FILTER DOUT0 AIN1 CONVERTER DOUT1 LOGIC DOUT2 AIN2+ ASYNCHRONOUS CTSD PROGRAMMABLE DIAGNOSTIC SAMPLE RATE DOUT3 MODULATOR DIGITAL FILTER AIN2 CONVERTER PIN/SPI MODE AIN3+ ASYNCHRONOUS CTSD PROGRAMMABLE DCLKRATE0/GPIO0 SAMPLE RATE MODULATOR DIGITAL FILTER AIN3 CONVERTER DCLKRATE1/GPIO1 DCLKRATE2/GPIO2 POWER MANAGEMENT PWRMODE/GPIO3 AGND1V8 FILTER0/GPIO4 DGND1V8 AD7134 FILTER1/GPIO5 LDO CLKGND FRAME0/GPIO6 LDO FRAME1/GPIO7 Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2020 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. IOGND REFGND AGND5 DGND5 REFCAP REFIN LDOIN CLKVDD XTAL1 DVDD1V8 XTAL2/CLKIN AVDD1V8 CLKSEL AVDD5 XCLKOUT DVDD5 PDN IOVDD RESET 22652-001AD7134 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Programming Output Data Rate and Clock ........................... 46 Applications ....................................................................................... 1 Programming Digital Filter....................................................... 49 Functional Block Diagram .............................................................. 1 Programming Data Interface .................................................... 49 Revision History ............................................................................... 2 Power Modes ............................................................................... 50 General Description ......................................................................... 3 Inherent Antialiasing Filter Modes .......................................... 51 Specifications ..................................................................................... 4 Dynamic Range Enhancement, Channel Averaging ................. 52 Timing Specifications ................................................................ 10 Calibration ....................................................................................... 53 Absolute Maximum Ratings .......................................................... 12 Offset Calibration ....................................................................... 53 Thermal Resistance .................................................................... 12 Gain Calibration ......................................................................... 53 ESD Caution ................................................................................ 12 Applications Information .............................................................. 54 Pin Configuration and Function Descriptions ........................... 13 Power Supply ............................................................................... 54 Typical Performance Characteristics ........................................... 17 Reference Noise Filtering .......................................................... 54 Terminology .................................................................................... 26 Multidevice Synchronization .................................................... 55 Theory of Operation ...................................................................... 28 Coherent Sampling..................................................................... 55 Continuous Time Sigma-Delta Modulator ............................. 28 Low Latency Digital Control Loop .......................................... 55 Easy to Drive Input and Reference ........................................... 28 Automatic Gain Control ............................................................ 56 Inherent Antialiasing Filter (AAF) .......................................... 29 Front-End Design Examples ..................................................... 56 Analog Front-End Design Simplification ............................... 30 Digital Interface .............................................................................. 58 Noise Performance and Resolution .............................................. 31 SPI Interface ................................................................................ 58 Circuit Information ........................................................................ 35 Data Interface .............................................................................. 59 Core Signal Chain ....................................................................... 35 Minimum I/O Mode .................................................................. 64 Analog Inputs .............................................................................. 35 Diagnostics ...................................................................................... 65 VCM Output ............................................................................... 35 Internal Fuse Integrity Check ................................................... 65 Reference Input ........................................................................... 36 Analog Input Overrange ........................................................... 66 Clock Input .................................................................................. 36 MCLK Counter ........................................................................... 66 XCLKOUT Output ..................................................................... 36 SPI Interface Monitoring ........................................................... 66 Power Options ............................................................................ 37 Memory Map Integrity Check .................................................. 66 Reset ............................................................................................. 37 ODR Input Frequency Check ................................................... 66 Asynchronous Sample Rate Converter .................................... 37 Digital Filter Overflow and Underflow ................................... 67 Digital Filters ............................................................................... 39 DCLK Error ................................................................................ 67 Quick Start Guide ........................................................................... 42 GPIO Functionality ........................................................................ 68 Standalone Mode ........................................................................ 43 Pin Error Reporting ................................................................... 68 Low Latency Synchronous Data Acquisition ............................. 43 Register Map (SPI Control) ........................................................... 69 Device Control ................................................................................ 44 Register Details ............................................................................... 71 Pin Control Mode ....................................................................... 44 Outline Dimensions ....................................................................... 86 SPI Control Mode ....................................................................... 45 Ordering Guide .......................................................................... 86 Multifunction Pins ..................................................................... 45 Device Configuration ..................................................................... 46 REVISION HISTORY 4/2020Revision 0: Initial Version Rev. 0 Page 2 of 86