32-Bit, 10 kSPS, Sigma-Delta ADC with 100 s Settling and True Rail-to-Rail Buffers Data Sheet AD7177-2 FEATURES GENERAL DESCRIPTION 32-bit data output The AD7177-2 is a 32-bit low noise, fast settling, multiplexed, Fast and flexible output rate: 5 SPS to 10 kSPS 2-/4-channel (fully/pseudo differential) - analog-to-digital Channel scan data rate of 10 kSPS/channel (100 s settling) converter (ADC) for low bandwidth inputs. It has a maximum Performance specifications channel scan rate of 10 kSPS (100 s) for fully settled data. The 19.1 noise free bits at 10 kSPS output data rates range from 5 SPS to 10 kSPS. 20.2 noise free bits at 2.5 kSPS The AD7177-2 integrates key analog and digital signal condition- 24.6 noise free bits at 5 SPS ing blocks to allow users to configure an individual setup for INL: 1 ppm of FSR each analog input channel in use. Each feature can be user selected 85 dB filter rejection of 50 Hz and 60 Hz with 50 ms settling on a per channel basis. Integrated true rail-to-rail buffers on the User configurable input channels analog inputs and external reference inputs provide easy to drive 2 fully differential channels or 4 single-ended channels high impedance inputs. The precision 2.5 V low drift (2 ppm/C) Crosspoint multiplexer band gap internal reference (with output reference buffer) adds On-chip 2.5 V reference (2 ppm/C drift) embedded functionality to reduce external component count. True rail-to-rail analog and reference input buffers Internal or external clock The digital filter allows simultaneous 50 Hz and 60 Hz rejection Power supply: AVDD1 AVSS = 5 V, AVDD2 = IOVDD = 2.5 V at a 27.27 SPS output data rate. The user can switch between to 5 V different filter options according to the demands of each Split supply with AVDD1/AVSS at 2.5 V channel in the application. The ADC automatically switches ADC current: 8.4 mA through each selected channel. Further digital processing Temperature range: 40C to +105C functions include offset and gain calibration registers, 3- or 4-wire serial digital interface (Schmitt trigger on SCLK) configurable on a per channel basis. Serial port interface (SPI), QSPI, MICROWIRE, and DSP The device operates with a 5 V AVDD1 supply, or with 2.5 V compatible AVDD1/AVSS, and 2 V to 5 V AVDD2 and IOVDD supplies. APPLICATIONS The specified operating temperature range is 40C to +105C. The AD7177-2 is available in a 24-lead TSSOP package. Process control: PLC/DCS modules Temperature and pressure measurement Medical and scientific multichannel instrumentation Chromatography FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 REGCAPA REF REF+ REFOUT IOVDD REGCAPD RAIL-TO-RAIL BUFFERED 1.8V REFERENCE 1.8V CROSSPOINT PRECISION LDO INPUT BUFFERS LDO MULTIPLEXER REFERENCE INT REF AIN0 AVDD RAIL-TO-RAIL CS ANALOG INPUT BUFFERS AIN1 SCLK SERIAL DIGITAL INTERFACE - ADC DIN AIN2 FILTER AND CONTROL DOUT/RDY AIN3 SYNC/ERROR GPIO AND XTAL AND INTERNAL MUX CLOCK OSCILLATOR AVSS AIN4 I/O CONTROL CIRCUITRY AD7177-2 TEMPERATURE SENSOR AVSS GPIO0 GPIO1 XTAL1 XTAL2/CLKIO DGND Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20152016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 12912-001AD7177-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 CRC Calculation ......................................................................... 42 Applications ....................................................................................... 1 Integrated Functions ...................................................................... 44 General Description ......................................................................... 1 General-Purpose I/O ................................................................. 44 Functional Block Diagram .............................................................. 1 External Multiplexer Control ................................................... 44 Revision History ............................................................................... 3 Delay ............................................................................................ 44 Specifications ..................................................................................... 4 24-Bit/32-Bit Conversions......................................................... 44 Timing Characteristics ................................................................ 7 DOUT RESET ........................................................................... 44 Absolute Maximum Ratings ............................................................ 9 Synchronization .......................................................................... 44 Thermal Resistance ...................................................................... 9 Error Flags ................................................................................... 45 ESD Caution .................................................................................. 9 DATA STAT ............................................................................... 45 Pin Configuration and Function Descriptions ........................... 10 IOSTRENGTH ........................................................................... 46 Typical Performance Characteristics ........................................... 12 Internal Temperature Sensor .................................................... 46 Noise Performance and Resolution .............................................. 18 Grounding and Layout .................................................................. 47 Getting Started ................................................................................ 19 Register Summary .......................................................................... 48 Power Supplies ............................................................................ 20 Register Details ............................................................................... 49 Digital Communication ............................................................. 20 Communications Register ......................................................... 49 AD7177-2 Reset .......................................................................... 21 Status Register ............................................................................. 50 Configuration Overview ........................................................... 21 ADC Mode Register ................................................................... 51 Circuit Description ......................................................................... 27 Interface Mode Register ............................................................ 52 Buffered Analog Input ............................................................... 27 Register Check ............................................................................ 53 Crosspoint Multiplexer .............................................................. 27 Data Register ............................................................................... 53 AD7177-2 Reference .................................................................. 28 GPIO Configuration Register ................................................... 54 Buffered Reference Input ........................................................... 29 ID Register................................................................................... 55 Clock Source ............................................................................... 29 Channel Register 0 ..................................................................... 55 Digital Filters ................................................................................... 30 Channel Register 1 to Channel Register 3 .............................. 56 Sinc5 + Sinc1 Filter ..................................................................... 30 Setup Configuration Register 0 ................................................ 57 Sinc3 Filter ................................................................................... 30 Setup Configuration Register 1 to Setup Configuration Register 3 ..................................................................................... 57 Single Cycle Settling ................................................................... 31 Filter Configuration Register 0 ................................................. 58 Enhanced 50 Hz and 60 Hz Rejection Filters ......................... 34 Filter Configuration Register 1 to Filter Configuration Operating Modes ............................................................................ 37 Register 3 ..................................................................................... 59 Continuous Conversion Mode ................................................. 37 Offset Register 0 ......................................................................... 59 Continuous Read Mode ............................................................. 38 Offset Register 1 to Offset Register 3 ....................................... 59 Single Conversion Mode ........................................................... 39 Gain Register 0............................................................................ 59 Standby and Power-Down Modes ............................................ 40 Gain Register 1 to Gain Register 3 ........................................... 59 Calibration ................................................................................... 40 Outline Dimensions ....................................................................... 60 Digital Interface .............................................................................. 41 Ordering Guide .......................................................................... 60 Checksum Protection................................................................. 41 Rev. B Page 2 of 60