Pin-Programmable, Ultralow Noise, 24-Bit, Sigma-Delta ADC for Bridge Sensors AD7191 FEATURES GENERAL DESCRIPTION Pin-programmable output rate The AD7191 is a low noise, complete analog front end for high Output data rate: 10 Hz, 50 Hz, 60 Hz, 120 Hz precision measurement applications. It contains a low noise, Pin-programmable PGA 24-bit sigma-delta (-) ADC. The on-chip low noise gain Gain: 1, 8, 64, 128 stage means that signals of small amplitude can be interfaced Pin-programmable power-down and reset directly to the ADC. It contains two differential analog inputs. RMS noise: 15 nV 10 Hz (gain = 128) The part also includes a temperature sensor that can be used for Up to 21.5 noise free bits (gain = 1) temperature compensation. Internal or external clock For ease-of-use, all the features of the AD7191 are controlled by Bridge power-down switch dedicated pins. The on-chip PGA has a gain of 1, 8, 64, or 128, Offset drift: 5 nV/C supporting a full-scale differential input of 5 V, 625 mV, Gain drift: 1 ppm/C 78 mV, or 39 mV. The output data rate can be programmed Specified drift over time to 10 Hz, 50 Hz, 60 Hz, or 120 Hz. Simultaneous 50 Hz and 60 Hz Simultaneous 50 Hz/60 Hz rejection rejection is obtained when the output data rate is set to 10 Hz Internal temperature sensor or 50 Hz 60 Hz only rejection is obtained when the output data Power supply: 3 V to 5.25 V rate is set to 60 Hz. The AD7191 can be operated with the Current: 4.35 mA internal clock, or an external clock can be used. Temperature range: 40C to +105C The part operates with a power supply of 3 V to 5.25 V. It Package: 24-lead TSSOP consumes a current of 4.35 mA. It is available in a 24-lead INTERFACE TSSOP package. 2-wire serial SPI, QSPI, and MICROWIRE compatible Schmitt trigger on SCLK APPLICATIONS Weigh scales Strain gauge transducers Pressure measurement Medical and scientific instrumentation FUNCTIONAL BLOCK DIAGRAM AV DV DD AGND DD DGND REFIN(+) REFIN() AD7191 DOUT/RDY AIN1 SERIAL SCLK AIN2 - INTERFACE MUX PGA PDOWN AIN3 ADC AND CONTROL CHAN LOGIC AIN4 CLKSEL BPDSW PGA2 TEMPERATURE CLOCK SENSOR CIRCUITRY PGA1 MCLK1 MCLK2 ODR2 ODR1 TEMP Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 08163-001AD7191 TABLE OF CONTENTS Features .............................................................................................. 1 Gain .............................................................................................. 15 Interface ............................................................................................. 1 Analog Input Channels .............................................................. 15 Applications ....................................................................................... 1 Temperature Sensor ................................................................... 16 General Description ......................................................................... 1 Power-Down (PDOWN) ........................................................... 16 Functional Block Diagram .............................................................. 1 Clock ............................................................................................ 16 Revision History ............................................................................... 2 Bipolar Configuration ................................................................ 16 Specif icat ions ..................................................................................... 3 Data Output Coding .................................................................. 16 Timing Characteristics ................................................................ 6 Bridge Power-Down Switch ...................................................... 16 Timing Diagram ........................................................................... 6 Reference ..................................................................................... 16 Absolute Maximum Ratings ............................................................ 7 Digital Interface .......................................................................... 17 ESD Caution .................................................................................. 7 Grounding and Layout .............................................................. 17 Pin Configuration and Function Descriptions ............................. 8 Applications Information .............................................................. 19 Typical Performance Characteristics ........................................... 10 Weigh Scales ................................................................................ 19 RMS Noise and Resolution Specifications .................................. 13 EMI Recommendations ............................................................. 19 ADC Circuit Information .............................................................. 14 Outline Dimensions ....................................................................... 20 O ver vie w ...................................................................................... 14 Ordering Guide .......................................................................... 20 Filter, Data Rate, and Settling Time ......................................... 14 REVISION HISTORY 5/09Rev. 0 to Rev A Changes to Gain Error Specification, Normal Mode Rejection Specification..................................................................... 3 Changes to Table 3 ............................................................................ 7 5/09Revision 0: Initial Version Rev. A Page 2 of 20