4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA AD7192 FEATURES Temperature measurement Chromatography RMS noise: 11 nV 4.7 Hz (gain = 128) PLC/DCS analog input modules 15.5 noise-free bits 2.4 kHz (gain = 128) Data acquisition Up to 22 noise-free bits (gain = 1) Medical and scientific instrumentation Offset drift: 5 nV/C Gain drift: 1 ppm/C GENERAL DESCRIPTION Specified drift over time The AD7192 is a low noise, complete analog front end for high 2 differential/4 pseudo differential input channels precision measurement applications. It contains a low noise, Automatic channel sequencer 24-bit sigma-delta (-) analog-to-digital converter (ADC). Programmable gain (1 to 128) The on-chip low noise gain stage means that signals of small Output data rate: 4.7 Hz to 4.8 kHz amplitude can be interfaced directly to the ADC. Internal or external clock The device can be configured to have two differential inputs or Simultaneous 50 Hz/60 Hz rejection four pseudo differential inputs. The on-chip channel sequencer 4 general-purpose digital outputs allows several channels to be enabled, and the AD7192 sequentially Power supply converts on each enabled channel. This simplifies communication AV : 3 V to 5.25 V DD DV : 2.7 V to 5.25 V with the part. The on-chip 4.92 MHz clock can be used as the DD Current: 4.35 mA clock source to the ADC or, alternatively, an external clock or Temperature range: 40C to +105C crystal can be used. The output data rate from the part can be Package: 24-lead TSSOP varied from 4.7 Hz to 4.8 kHz. The device has two digital filter options. The choice of filter INTERFACE affects the rms noise/noise-free resolution at the programmed 3-wire serial output data rate, the settling time, and the 50 Hz/60 Hz SPI, QSPI, MICROWIRE, and DSP compatible rejection. For applications that require all conversions to be Schmitt trigger on SCLK settled, the AD7192 includes a zero latency feature. APPLICATIONS The part operates with a power supply from 3 V to 5.25 V. It Weigh scales consumes a current of 4.35 mA. It is housed in a 24-lead TSSOP Strain gage transducers package. Pressure measurement FUNCTIONAL BLOCK DIAGRAM AGND AV DV DGND REFIN1(+) REFIN1() DD DD REFERENCE DETECT AD7192 AV DD AIN1 AIN2 AIN3 DOUT/RDY SERIAL AIN4 INTERFACE MUX - DIN AINCOM PGA AND ADC CONTROL SCLK LOGIC CS SYNC AGND TEMP P3 SENSOR P2 BPDSW CLOCK CIRCUITRY AGND MCLK1 MCLK2 P0/REFIN2() P1/REFIN2(+) Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07822-001AD7192 TABLE OF CONTENTS Features .............................................................................................. 1 Offset Register ............................................................................ 24 Interface ............................................................................................. 1 Full-Scale Register ...................................................................... 24 Applications ....................................................................................... 1 ADC Circuit Information .............................................................. 25 General Description ......................................................................... 1 Overview ..................................................................................... 25 Functional Block Diagram .............................................................. 1 Filter, Output Data Rate, and Settling Time ........................... 25 Revision History ............................................................................... 2 Digital Interface .......................................................................... 28 Specif icat ions ..................................................................................... 3 Circuit Description......................................................................... 32 Timing Characteristics ..................................................................... 7 Analog Input Channel ............................................................... 32 Circuit and Timing Diagrams ..................................................... 7 Programmable Gain Array (PGA) ........................................... 32 Absolute Maximum Ratings ............................................................ 9 Bipolar/Unipolar Configuration .............................................. 32 Thermal Resistance ...................................................................... 9 Data Output Coding .................................................................. 32 ESD Caution .................................................................................. 9 Clock ............................................................................................ 32 Pin Configuration and Function Descriptions ........................... 10 Burnout Currents ....................................................................... 33 Typical Performance Characteristics ........................................... 12 Reference ..................................................................................... 33 RMS Noise and Resolution ............................................................ 14 Reference Detect ......................................................................... 33 4 Sinc Chop Disabled ................................................................... 14 Reset ............................................................................................. 34 3 Sinc Chop Disabled ................................................................... 15 System Synchronization ............................................................ 34 4 Sinc Chop Enabled .................................................................... 16 Temperature Sensor ................................................................... 34 3 Sinc Chop Enabled .................................................................... 17 Bridge Power-Down Switch ...................................................... 34 On-Chip Registers .......................................................................... 18 Logic Outputs ............................................................................. 34 Communications Register ......................................................... 18 Enable Parity ............................................................................... 35 Status Register ............................................................................. 19 C a l ibr at ion ................................................................................... 35 Mode Register ............................................................................. 19 Grounding and Layout .............................................................. 36 Configuration Register .............................................................. 21 Applications Information .............................................................. 37 Data Register ............................................................................... 23 Weigh Scales ................................................................................ 37 ID Register ................................................................................... 23 Outline Dimensions ....................................................................... 38 GPOCON Register ..................................................................... 24 Ordering Guide .......................................................................... 38 REVISION HISTORY 5/09Rev. 0 to Rev. A Change to Gain Error Specification ............................................... 3 Changes to Table 3 ............................................................................ 9 5/09Revision 0: Initial Version Rev. A Page 2 of 40