8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA Data Sheet AD7194 FEATURES Pressure measurement Temperature measurement Fast settling filter option Flow measurement 8 differential/16 pseudo differential input channels Weigh scales RMS noise: 11 nV at 4.7 Hz (gain = 128) Chromatography 15.5 noise-free bits at 2.4 kHz (gain = 128) Medical and scientific instrumentation Up to 22 noise-free bits (gain = 1) Offset drift: 5 nV/C GENERAL DESCRIPTION Gain drift: 1 ppm/C The AD7194 is a low noise, complete analog front end for high Programmable gain (1 to 128) precision measurement applications. It contains a low noise, Output data rate: 4.7 Hz to 4.8 kHz 24-bit sigma-delta (-) analog-to-digital converter (ADC). Internal or external clock The on-chip low noise gain stage means that signals of small Simultaneous 50 Hz/60 Hz rejection amplitude can interface directly to the ADC. 4 general-purpose digital outputs The device can be configured to have eight differential inputs or Power supply sixteen pseudo differential inputs. The on-chip 4.92 MHz clock AV : 3 V to 5.25 V DD can be used as the clock source to the ADC or, alternatively, an DV : 2.7 V to 5.25 V DD external clock or crystal can be used. The output data rate from Current: 4.65 mA Temperature range: 40C to +105C the part can be varied from 4.7 Hz to 4.8 kHz. Package: 32-lead LFCSP The device has a very flexible digital filter, including a fast Interface settling option. Variables such as output data rate and settling 3-wire serial time are dependent on the option selected. For applications that SPI, QSPI, MICROWIRE, and DSP compatible require all conversions to be settled, the AD7194 includes zero Schmitt trigger on SCLK latency. APPLICATIONS The part operates with a power supply from 3 V to 5.25 V. It consumes a current of 4.65 mA, and it is housed in a 32-lead PLC/DCS analog input modules LFCSP package. Data acquisition Strain gage transducers FUNCTIONAL BLOCK DIAGRAM AV AGND DV DGND REFIN1(+) REFIN1() DD DD REFERENCE DETECT AD7194 AIN1/P3 AV DD AIN2/P2 AIN3/P1/REFIN2(+) DOUT/RDY AIN4/P0/REFIN2() SERIAL INTERFACE AIN5 MUX DIN - PGA AND ADC CONTROL SCLK LOGIC AIN16 CS AINCOM AGND CLOCK TEMP CIRCUITRY SENSOR MCLK1 MCLK2 Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092017 Analog Devices, Inc. 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Technical Support www.analog.com 08566-001AD7194 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Programmable Gain Array (PGA) ........................................... 30 Applications ....................................................................................... 1 Reference ..................................................................................... 30 General Description ......................................................................... 1 Reference Detect ......................................................................... 31 Functional Block Diagram .............................................................. 1 Bipolar/Unipolar Configuration .............................................. 31 Revision History ............................................................................... 2 Data Output Coding .................................................................. 31 Specifications ..................................................................................... 3 Burnout Currents ....................................................................... 31 Timing Characteristics ................................................................ 7 Digital Interface .......................................................................... 32 Absolute Maximum Ratings ............................................................ 9 Reset ............................................................................................. 36 Thermal Resistance ...................................................................... 9 System Synchronization ............................................................ 36 ESD Caution .................................................................................. 9 Enable Parity ............................................................................... 36 Pin Configuration and Function Descriptions ........................... 10 Clock ............................................................................................ 36 Typical Performance Characteristics ........................................... 12 Temperature Sensor ................................................................... 36 RMS Noise and Resolution............................................................ 15 Logic Outputs ............................................................................. 37 4 Sinc Chop Disabled ................................................................... 15 Calibration................................................................................... 37 3 Sinc Chop Disabled ................................................................... 16 Digital Filter .................................................................................... 39 4 Fast Settling ................................................................................. 17 Sinc Filter (Chop Disabled) ..................................................... 39 3 On-Chip Registers .......................................................................... 18 Sinc Filter (Chop Disabled) ..................................................... 41 4 Communications Register ......................................................... 19 Chop Enabled (Sinc Filter) ...................................................... 43 3 Status Register ............................................................................. 20 Chop Enabled (Sinc Filter) ...................................................... 45 4 Mode Register ............................................................................. 21 Fast Settling Mode (Sinc Filter) ............................................... 46 3 Configuration Register .............................................................. 24 Fast Settling Mode (Sinc Filter) ............................................... 48 Data Register ............................................................................... 27 Fast Settling Mode (Chop Enabled) ......................................... 50 ID Register ................................................................................... 27 Summary of Filter Options ....................................................... 51 GPOCON Register ..................................................................... 27 Grounding and Layout .................................................................. 52 Offset Register ............................................................................. 28 Applications Information .............................................................. 53 Full-Scale Register ...................................................................... 28 Flowmeter .................................................................................... 53 ADC Circuit Information .............................................................. 29 Outline Dimensions ....................................................................... 54 Overview ...................................................................................... 29 Ordering Guide .......................................................................... 54 Analog Input Channel ............................................................... 30 REVISION HISTORY 6/2017Rev. A to Rev. B 3/2013Rev. 0 to Rev. A Changed CP-32-11 to CP-32-12 .................................. Throughout Changes to Pin 26, Table 5 ............................................................ 11 Changes to Table 5 .......................................................................... 11 Changes to Table 21 ....................................................................... 25 Updated Outline Dimensions ....................................................... 54 Changes to Analog Inputs Section ............................................... 29 Changes to Ordering Guide .......................................................... 54 Changes to Data Output Coding Section .................................... 31 10/2009Revision 0: Initial Version Rev. B Page 2 of 54