Dual, Simultaneous Sampling, 16-Bit/14-Bit, 4 MSPS SAR ADCs, Differential Inputs Data Sheet AD7380/AD7381 FEATURES GENERAL DESCRIPTION 16-bit/14-bit ADC family The AD7380/AD7381 are a 16-bit and 14-bit pin-compatible Dual simultaneous sampling family of dual simultaneous sampling, high speed, low power, Fully differential analog inputs successive approximation register (SAR) analog-to-digital 4 MSPS throughput conversion rate converters (ADCs) that operate from a 3.0 V to 3.6 V power SNR (typical) supply and feature throughput rates up to 4 MSPS. The analog 92.5 dB, V = 3.3 V external at AD7380 (16-bit) REF input type is differential, accepts a wide common-mode input 85.4 dB, V = 3.3 V external at AD7381 (14-bit) REF CS voltage, and is sampled and converted on the falling edge of . 101 dB with 16 OSR An integrated on-chip oversampling block improves dynamic On-chip oversampling function range and reduces noise at lower bandwidths. A buffered Resolution boost function internal 2.5 V reference is included. Alternatively, an external INL (maximum) reference up to 3.3 V can be used. 2.0 LSBs at 16-bit The conversion process and data acquisition use standard control 1.0 LSB at 14-bit inputs allowing simple interfacing to microprocessors or digital 2.5 V internal reference signal processors (DSPs). The device is compatible with 1.8 V, High speed serial interface 2.5 V, and 3.3 V interfaces using the separate logic supply. 40C to +125C operation 16-lead LFCSP, 3 mm 3 mm The AD7380/AD7381 are available in a 16-lead lead frame chip Wide common-mode range scale package (LFCSP) with operation specified from 40C to Alert function +125C. APPLICATIONS PRODUCT HIGHLIGHTS Motor control position feedback 1. Dual simultaneous sampling and conversion with two Motor control current sense complete ADC functions. Sonar 2. Pin-compatible product family. Power quality 3. High 4 MSPS throughput rate. Data acquisition systems 4. Space saving 3 mm 3 mm LFCSP. Erbium doped fiber amplifier (EDFA) applications 5. An integrated oversampling block to increase dynamic I and Q demodulation range, reduce noise, and reduce SCLK speed requirements. 6. Differential analog inputs with wide common-mode range. 7. Small sampling capacitor reduces amplifier drive burden. FUNCTIONAL BLOCK DIAGRAM 3.3V 3.3V 1F 1F (A A+ AND A A) IN IN V V CC LOGIC V REF R C1 A A+ IN 0V OVER- C2 ADC A SDOA R A A SAMPLING IN V REF C1 REFIO 0V OSC REFCAP GND SCLK REF DIGITAL CONTROL (A B+ AND A B) IN IN SDI CONTROLLER LOGIC REGCAP LDO CS V REF R C1 A B+ IN 0V OVER- C2 ADC B SDOB/ALERT A B R IN SAMPLING V REF C1 AD7380/AD7381 0V GND Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 16871-001AD7380/AD7381 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Resolution Boost ........................................................................ 20 Applications ....................................................................................... 1 Alert ............................................................................................. 20 General Description ......................................................................... 1 Power Modes ............................................................................... 21 Product Highlights ........................................................................... 1 Internal and External Reference ............................................... 21 Functional Block Diagram .............................................................. 1 Software Reset ............................................................................. 21 Revision History ............................................................................... 2 Diagnostic Self Test .................................................................... 21 Specif icat ions ..................................................................................... 3 Interface ........................................................................................... 22 Timing Specifications .................................................................. 6 Reading Conversion Results ..................................................... 22 Absolute Maximum Ratings ............................................................ 8 Low Latency Readback .............................................................. 23 Thermal Resistance ...................................................................... 8 Reading from Device Registers ................................................ 24 ESD Caution .................................................................................. 8 Writing to Device Registers ...................................................... 24 Pin Configuration and Function Descriptions ............................. 9 CRC .............................................................................................. 25 Typical Performance Characteristics ........................................... 10 Registers ........................................................................................... 27 Terminology .................................................................................... 13 Addressing Registers .................................................................. 27 Theory of Operation ...................................................................... 14 CONFIGURATION1 Register ................................................. 28 Circuit Information .................................................................... 14 CONFIGURATION2 Register ................................................. 29 Converter Operation .................................................................. 14 ALERT Register .......................................................................... 29 Analog Input Structure .............................................................. 14 ALERT LOW THRESHOLD Register .................................. 30 ADC Transfer Function ............................................................. 15 ALERT HIGH THRESHOLD Register ................................. 30 Applications Information .............................................................. 16 Outline Dimensions ....................................................................... 31 Power Supply ............................................................................... 16 Ordering Guide .......................................................................... 31 Modes of Operation ....................................................................... 18 Oversampling .............................................................................. 18 REVISION HISTORY 11/2019Rev. 0 to Rev. A Changes to Normal Average Oversampling Section, Updated Title ..................................................................................... 1 Table 10, and Figure 32 .................................................................. 18 Changes to Features Section, Applications Section, Changes to Rolling Average Oversampling Section and Figure 1 ....................................................................................... 1 and Figure 33 ................................................................................... 19 Changes to Table 1 ............................................................................ 3 Changes to Resolution Boost Section .......................................... 20 Changes to Table 2 ............................................................................ 4 Added Figure 36 Renumbered Sequentially .............................. 21 Changes to Aperture Delay Match Parameter, Table 3 and Change to Figure 37 and Table 12 ................................................ 22 V Noise Parameter, Table 3 ......................................................... 5 Changes to Serial 2-Wire Mode Section, Resolution Boost REF Changes to Table 4 ............................................................................ 6 Mode Section, Figure 38, and Figure 40 ...................................... 23 Change to Thermal Resistance Section ......................................... 8 Changes to Figure 41 and Figure 42............................................. 24 Changes to Figure 43 ...................................................................... 26 Change to Pin 9 Description, Table 7 ............................................ 9 Changes to Figure 11 Caption ....................................................... 10 Changes to Table 14 and Table 16 ................................................ 27 Changes to Figure 15 Caption, Figure 18, Figure 19, Change to CONFIGURATION1 Register Section and Figure 20 ................................................................................... 11 and Table 17 .................................................................................... 28 Changes to Terminology Section.................................................. 13 Changes to CONFIGURATION2 Register Section Change to ADC Transfer Function Section ................................ 15 ALERT and Register Section ......................................................... 29 Changes to Applications Information Section and Changes to ALERT LOW THRESHOLD Register Section, Power Supply Section ..................................................................... 16 Table 20, ALERT HIGH THRESHOLD Register Section, Added Table 9 Renumbered Sequentially .................................. 16 and Table 21 ................................................................................... 30 Changes to Figure 31 ...................................................................... 17 Changes to Ordering Guide .......................................................... 31 1/2019Revision 0: Initial Version Rev. A Page 2 of 31