Differential Input, 1 MSPS 10-Bit and 12-Bit ADCs in an 8-Lead SOT-23 Data Sheet AD7440/AD7450A FEATURES FUNCTIONAL BLOCK DIAGRAM V DD Fast throughput rate: 1 MSPS Specified for V of 3 V and 5 V DD Low power at max throughput rate 4 mW max at 1 MSPS with 3 V supplies V IN+ 12-BIT SUCCESSIVE T/H 9.25 mW max at 1 MSPS with 5 V supplies APPROXIMATION V IN ADC Fully differential analog input V REF Wide input bandwidth 70 dB SINAD at 100 kHz input frequency Flexible power/serial clock speed management No pipeline delays SCLK High speed serial interface SDATA AD7440/AD7450A CONTROL LOGIC SPI/QSPI/MICROWIRE/DSP compatible CS Power-down mode: 1 A max 8-lead SOT-23 and MSOP packages GND APPLICATIONS Figure 1. Transducer interface Battery-powered systems Data acquisition systems Portable instrumentation Motor control on the falling edge of CS the conversion is also initiated at this GENERAL DESCRIPTION point. The SAR architecture of these parts ensures that there are 1 no pipeline delays. The AD7440 and the AD7450A use advanced The AD7440/AD7450A are 10-bit and 12-bit high speed, low design techniques to achieve very low power dissipation at high power, successive approximation (SAR) analog-to-digital throughput rates. converters with a fully differential analog input. These parts operate from a single 3 V or 5 V power supply and use PRODUCT HIGHLIGHTS advanced design techniques to achieve very low power 1. Operation with either 3 V or 5 V power supplies. dissipation at throughput rates up to 1 MSPS. The SAR 2. High throughput with low power consumption. architecture of these parts ensures that there are no pipeline With a 3 V supply, the AD7440/AD7450A offer 4 mW delays. max power consumption for 1 MSPS throughput. The parts contain a low noise, wide bandwidth, differential 3. Fully differential analog input. track-and-hold amplifier (T/H) that can handle input 4. Flexible power/serial clock speed management. frequencies up to 3.5 MHz. The reference voltage is applied The conversion rate is determined by the serial clock, externally to the VREF pin and can be varied from 100 mV to allowing the power to be reduced as the conversion time 3.5 V depending on the power supply and what suits the is reduced through the serial clock speed increase. These application. The value of the reference voltage determines the parts also feature a shutdown mode to maximize power common-mode voltage range of the part. With this truly efficiency at lower throughput rates. differential input structure and variable reference input, the 5. Variable voltage reference input. user can select a variety of input ranges and bias points. 6. No pipeline delay. The conversion process and data acquisition are controlled 7. Accurate control of the sampling instant via a CS input and using CS and the serial clock, allowing the device to interface once-off conversion control. with microprocessors or DSPs. The input signals are sampled 1 8. ENOB > eight bits typically with 100 mV reference. Protected by U.S. Patent Number 6,681,332. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20032015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 03051-A-001AD7440/AD7450A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Connection Diagram ................................................... 16 Applications ....................................................................................... 1 Analog Input ............................................................................... 16 General Description ......................................................................... 1 Driving Differential Inputs ....................................................... 18 Functional Block Diagram .............................................................. 1 Digital Inputs .............................................................................. 19 Product Highlights ........................................................................... 1 Reference ..................................................................................... 19 Revision History ............................................................................... 2 Single-Ended Operation ............................................................ 20 AD7440Specifications .................................................................... 3 Serial Interface ............................................................................ 21 AD7450ASpecifications ................................................................. 5 Modes of Operation ....................................................................... 23 Timing Specifications ....................................................................... 7 Normal Mode .............................................................................. 23 Absolute Maximum Ratings ............................................................ 8 Power-Down Mode .................................................................... 23 ESD Caution .................................................................................. 8 Power-Up Time .......................................................................... 24 Pin Configurations and Function Descriptions ........................... 9 Power vs. Throughput Rate ....................................................... 24 Terminology .................................................................................... 10 Grounding and Layout Hints.................................................... 25 AD7440/AD7450ATypical Performance Characteristics ....... 12 Evaluating the AD7440/AD7450A Performance ................... 25 Circuit Information ........................................................................ 15 Outline Dimensions ....................................................................... 26 Converter Operation .................................................................. 15 Ordering Guide .......................................................................... 27 ADC Transfer Function ............................................................. 15 REVISION HISTORY 7/15Rev. C to Rev. D 2/04Rev. A to Rev. B Changed F to f .................................................... Throughout Added Patent Note ............................................................................ 1 SCLK SCLK Changes to Figure 34 ...................................................................... 18 Changes to Power vs. Throughput Rate Section ........................ 24 1/04Rev. 0 to Rev. A Deleted Microprocessor and DSP Interfacing Section, Updated Format .................................................................. Universal AD7440/AD7450A to ADSP-21xx Section, Table 7, and Figure Changes to General Description ..................................................... 1 45 Renumbered Sequentially ....................................................... 25 Changes to Table 1 Footnotes .......................................................... 3 Deleted AD7440/AD7450A to TMS320C5x/C54x Section, Changes to Table 2 Footnotes .......................................................... 5 Changes to Table 3 Footnotes .......................................................... 7 Figure 46, AD7440/AD7450A to DSP56xxx Section, and Figure 47 .......................................................................................... 26 Updated Outline Dimensions ....................................................... 27 8/03Revision 0: Initial Version Changes to Ordering Guide .......................................................... 28 9/05Rev. B to Rev. C Changes to Ordering Guide .......................................................... 28 Rev. D Page 2 of 27