8-Channel, 24-Bit, Simultaneous Sampling ADC with Power Scaling, 110.8 kHz Bandwidth Data Sheet AD7768-CHIPS FEATURES Wideband brick wall filter: 0.005 dB pass-band ripple to Precision ac and dc performance 102.4 kHz 8-channel simultaneous sampling Analog input precharge buffers 256 kSPS maximum ADC ODR per channel Power supply 108 dB dynamic range AVDD1 = 5.0 V, AVDD2 = 2.25 V to 5.0 V 120 dB THD, typical IOVDD = 2.5 V to 3.3 V or IOVDD = 1.8 V 2 ppm of FSR INL, 50 V offset error, 30 ppm of FSR Temperature range: 40C to +105C gain error APPLICATIONS Optimized power dissipation vs. noise vs. input bandwidth Data acquisition systems: USB/PXI/Ethernet Selectable power, speed, and input bandwidth Instrumentation and industrial control loops Input bandwidth range up to 110.8 kHz (3 dB bandwidth) Audio testing and measurement Programmable input bandwidth/sampling rates Vibration and asset condition monitoring CRC error checking on data interface 3-phase power quality analysis Daisy-chaining Sonar Linear phase digital filter EEG/EMG/ECG Low latency sinc5 filter FUNCTIONAL BLOCK DIAGRAM AVDD1A, AVDD2A, REGCAPA, AVDD1B REFx+ REFx AVDD2B REGCAPB DGND IOVDD DREGCAP BUFFERED VCM PRECHARGE 1.8V 1.8V REFERENCE LDO LDO VCM VCM 8 BUFFERS SYNC IN SYNC OUT START AIN0+ OFFSET, - DIGITAL RESET CH 0 GAIN PHASE ADC FILTER CORRECTION AIN0 FORMAT1 ENGINE FORMAT0 AIN1+ OFFSET, - CH 1 GAIN PHASE ADC AIN1 CORRECTION ADC OUTPUT DRDY SINC5 DATA AIN2+ OFFSET, LOW LATENCY - SERIAL DCLK CH 2 GAIN PHASE FILTER ADC INTERFACE AIN2 DOUT0 CORRECTION DOUT1 AIN3+ OFFSET, - CH 3 GAIN PHASE ADC AIN3 CORRECTION DOUT7 AIN4+ OFFSET, - WIDEBAND CH 4 GAIN PHASE ADC LOW RIPPLE AIN4 CORRECTION FILTER AIN5+ OFFSET, - CH 5 GAIN PHASE ADC AIN5 CORRECTION ST0/CS ST1/SCLK AIN6+ OFFSET, SPI - CH 6 GAIN PHASE CONTROL DEC0/SDO ADC AIN6 CORRECTION INTERFACE DEC1/SDI AIN7+ OFFSET, - CH 7 PIN/SPI GAIN PHASE ADC CORRECTION AIN7 AD7768-CHIPS AVSS XTAL2/MCLK XTAL1 MODE3/GPIO3 FILTER/GPIO4 TO MODE0/GPIO0 Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 2021 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. 25518-001AD7768-CHIPS Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 1.8 V IOVDD Timing Specifications ...................................... 13 Applications ...................................................................................... 1 Absolute Maximum Ratings ......................................................... 17 Functional Block Diagram .............................................................. 1 ESD Caution ............................................................................... 17 Revision History ............................................................................... 2 Pin Configuration and Function Descriptions .......................... 18 General Description ......................................................................... 3 Outline Dimensions ....................................................................... 21 Specifications .................................................................................... 4 Die Specifications and Assembly Recommendations ........... 21 1.8 V IOVDD Specifications ....................................................... 9 Ordering Guide .......................................................................... 22 Timing Specifications ................................................................ 12 REVISION HISTORY 3/2021Revision 0: Initial Version Rev. 0 Page 2 of 22