8-Channel, 24-Bit, Simultaneous Sampling ADC Data Sheet AD7770 The analog inputs accept unipolar (0 V to VREF) or true bipolar FEATURES (VREF/2) analog input signals with 3.3 V or 1.65 V analog 8-channel, 24-bit simultaneous sampling analog-to-digital supply voltages, respectively for PGAGAIN = 1. The analog inputs converter (ADC) can be configured to accept true differential, pseudo differential, Single-ended or true differential inputs or single-ended signals to match different sensor output Programmable gain amplifier (PGA) per channel (gains of configurations. 1, 2, 4, and 8) Low dc input current Each channel contains a PGA, an ADC modulator and a 4 nA (differential) and 8 nA (single-ended) sinc3, low latency digital filter. An SRC is provided to allow fine Up to 32 kSPS output data rate (ODR) per channel resolution control over the AD7770 ODR. This control can be Programmable ODRs and bandwidth used in applications where the ODR resolution is required to Sample rate converter (SRC) for coherent sampling maintain coherency with 0.01 Hz changes in the line frequency. 6 Sampling rate resolution up to 15.2 10 SPS The SRC is programmable through the serial port interface (SPI). Low latency sinc3 filter path The AD7770 implements two different interfaces: a data output Adjustable phase synchronization interface and SPI control interface. The ADC data output interface Internal 2.5 V reference is dedicated to transmitting the ADC conversion results from Two power modes optimizing power dissipation and the AD7770 to the processor. The SPI writes to and reads from performance: high resolution mode and low power mode the AD7770 configuration registers and for the control and Low resolution successive approximation register (SAR) ADC reading of data from the SAR ADC. The SPI can also be for system and chip diagnostics configured to output the - conversion data. Power supply The AD7770 includes a 12-bit SAR ADC. This ADC can be Bipolar (1.65 V) or unipolar (3.3 V) supplies used for AD7770 diagnostics without having to decommission Digital input/output (I/O) supply: 1.8 V to 3.6 V one of the - ADC channels dedicated to system measurement Performance temperature range: 40C to +105C functions. With the use of an external multiplexer, which can be Functional temperature range: 40C to +125C controlled through the three general-purpose input/output pins Performance (GPIOs), and signal conditioning, the SAR ADC can validate Combined ac and dc performance the - ADC measurements in applications where functional 103 dB dynamic range at 32 kSPS in high resolution mode safety is required. In addition, the AD7770 SAR ADC includes 109 dB total harmonic distortion (THD) an internal multiplexer to sense internal nodes. 9 ppm of FSR integral nonlinearity (INL) The AD7770 contains a 2.5 V reference and reference buffer. The 15 V offset error 0.1% FS gain error reference has a typical temperature coefficient of 10 ppm/C. 10 ppm/C typical temperature coefficient The AD7770 offers two modes of operation: high resolution mode and low power mode. High resolution mode provides a higher APPLICATIONS dynamic range while consuming 10.75 mW per channel low Protection relays power mode consumes just 3.37 mW per channel at a reduced General-purpose data acquisition dynamic range specification. Industrial process control The specified operating temperature range is 40C to +105C, GENERAL DESCRIPTION although the device is operational up to +125C. The AD7770 is an 8-channel, simultaneous sampling ADC. Eight Note that throughout this data sheet, certain terms are used to full sigma-delta (-) ADCs are on chip. The AD7770 provides refer to either the multifunction pins or a range of pins. The multi- a low input current to allow direct sensor connection. Each input function pins, such as DCLK0/SDO, are referred to either by the channel has a programmable gain stage allowing gains of 1, 2, 4, entire pin name or by a single function of the pin, for example, and 8 to map lower amplitude sensor outputs into the full-scale DCLK0, when only that function is relevant. In the case of ranges ADC input range, maximizing the dynamic range of the signal of pins, AVSSx refers to the following pins: AVSS1A, AVSS1B, chain. The AD7770 accepts a V voltage from 1 V up to 3.6 V. REF AVSS2A, AVSS2B, AVSS3, and AVSS4. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20162020 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com AD7770 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 - Output Data............................................................................. 51 Applications ....................................................................................... 1 ADC Conversion OutputHeader and Data ........................ 51 General Description ......................................................................... 1 Sample Rate Converter (SRC) (SPI Control Mode) .............. 52 Revision History ............................................................................... 4 Data Output Interface ................................................................ 53 Functional Block Diagram .............................................................. 5 Calculating the CRC Checksum .............................................. 58 Specifications ..................................................................................... 6 Register Summary .......................................................................... 60 DOUTx Timing Characterististics ........................................... 10 Register Details ............................................................................... 64 SPI Timing Characterististics ................................................... 11 Channel 0 Configuration Register ........................................... 64 Synchronization Pins and Reset Timing Characteristics ...... 12 Channel 1 Configuration Register ........................................... 64 SAR ADC Timing Characterististics ....................................... 13 Channel 2 Configuration Register ........................................... 65 GPIO SRC Update Timing Characterististics ......................... 13 Channel 3 Configuration Register ........................................... 65 Absolute Maximum Ratings .......................................................... 14 Channel 4 Configuration Register ........................................... 66 Thermal Resistance .................................................................... 14 Channel 5 Configuration Register ........................................... 66 ESD Caution ................................................................................ 14 Channel 6 Configuration Register ........................................... 67 Pin Configuration and Function Descriptions ........................... 15 Channel 7 Configuration Register ........................................... 67 Typical Performance Characteristics ........................................... 18 Disable Clocks to ADC Channel Register .............................. 68 Terminology .................................................................................... 31 Channel 0 Sync Offset Register ................................................ 68 Theory of Operation ...................................................................... 33 Channel 1 Sync Offset Register ................................................ 68 Analog Inputs .............................................................................. 33 Channel 2 Sync Offset Register ................................................ 68 Transfer Function ....................................................................... 34 Channel 3 Sync Offset Register ................................................ 69 Core Signal Chain ....................................................................... 35 Channel 4 Sync Offset Register ................................................ 69 Capacitive PGA ........................................................................... 35 Channel 5 Sync Offset Register ................................................ 69 Internal Reference and Reference Buffers ............................... 35 Channel 6 Sync Offset Register ................................................ 69 Integrated LDOs ......................................................................... 36 Channel 7 Sync Offset Register ................................................ 69 Clocking and Sampling .............................................................. 36 General User Configuration 1 Register ................................... 70 Digital Reset and Synchronization Pins .................................. 36 General User Configuration 2 Register ................................... 70 Digital Filtering ........................................................................... 37 General User Configuration 3 Register ................................... 71 Shutdown Mode .......................................................................... 37 Data Output Format Register ................................................... 72 Controlling the AD7770 ............................................................ 38 Main ADC Meter and Reference Mux Control Register ...... 73 Pin Control Mode ....................................................................... 38 Global Diagnostics Mux Register ............................................. 74 SPI Control .................................................................................. 40 GPIO Configuration Register ................................................... 74 Digital SPI .................................................................................... 43 GPIO Data Register .................................................................... 75 RMS Noise and Resolution ............................................................ 46 Buffer Configuration 1 Register ............................................... 75 High Resolution Mode ............................................................... 46 Buffer Configuration 2 Register ............................................... 75 Low Power Mode ........................................................................ 46 Channel 0 Offset Upper Byte Register..................................... 76 Diagnostics and Monitoring ......................................................... 47 Channel 0 Offset Middle Byte Register ................................... 76 Self Diagnostics Error ................................................................ 47 Channel 0 Offset Lower Byte Register ..................................... 76 Monitoring Using the AD7770 SAR ADC (SPI Control Channel 0 Gain Upper Byte Register ....................................... 76 Mode) ........................................................................................... 48 Channel 0 Gain Middle Byte Register ..................................... 76 - ADC Diagnostics (SPI Control Mode) ............................ 50 Channel 0 Gain Lower Byte Register ....................................... 77 Rev. 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