8-Channel, 24-Bit, Simultaneous Sampling ADC Data Sheet AD7771 voltage from 1 V up to 3.6 V. The analog inputs accept unipolar FEATURES (0 V to VREF) or true bipolar (VREF/2 V) analog input signals with 8-channel, 24-bit simultaneous sampling ADC 3.3 V or 1.65 V analog supply voltages, respectively. The analog Single-ended or true differential inputs inputs can be configured to accept true differential or single-ended PGA per channel (gains of 1, 2, 4, and 8) signals to match different sensor output configurations. Low dc input current 4 nA (differential)/8 nA (single-ended) Each channel contains an ADC modulator and a sinc3/sinc5, low Up to 128 kSPS ODR per channel latency digital filter. A sample rate converter (SRC) is provided to Programmable ODRs and bandwidth allow fine resolution control over the AD7771 output data rate SRC for coherent sampling (ODR). This control can be used in applications where the ODR 6 Sampling rate resolution up to 15.2 10 SPS resolution is required to maintain coherency with 0.01 Hz Low latency sinc3 and sinc5 filter paths changes in the line frequency. The SRC is programmable through Adjustable phase synchronization the serial port interface (SPI). The AD7771 implements two Internal 2.5 V reference different interfaces: a data output interface and SPI control Two power modes interface. The ADC data output interface is dedicated to trans- High resolution mode mitting the ADC conversion results from the AD7771 to the Low power mode processor. The SPI writes to and reads from the AD7771 Optimizes power dissipation and performance configuration registers and for the control and reading of data Low resolution SAR ADC for system and chip diagnostics from the successive approximation register (SAR) ADC. The SPI Power supply can also be configured to output the - conversion data. Bipolar (1.65 V) or unipolar (3.3 V) supplies The AD7771 includes a 12-bit SAR ADC. This ADC can be used Digital I/O supply: 1.8 V to 3.6 V for AD7771 diagnostics without having to decommission one of Performance temperature range: 40C to +105C the - ADC channels dedicated to system measurement func- Functional temperature range: 40C to +125C tions. With the use of an external multiplexer, which can be Performance controlled through the three general-purpose input/output pins Combined ac and dc performance (GPIOs), and signal conditioning, the SAR ADC can validate 107 dB SNR/dynamic range at 32 kSPS in high resolution the - ADC measurements in applications where functional mode (sinc5) safety is required. In addition, the AD7771 SAR ADC includes 109 dB THD an internal multiplexer to sense internal nodes. 8 ppm of FSR INL The AD7771 contains a 2.5 V reference and reference buffer. The 15 V offset error 0.1% FS gain error reference has a typical temperature coefficient of 10 ppm/C. 10 ppm/C typical temperature coefficient The AD7771 offers two modes of operation: high resolution mode and low power mode. High resolution mode provides a APPLICATIONS higher dynamic range while consuming 16.6 mW per channel Power quality and measurement applications low power mode consumes only 5.25 mW per channel at a General-purpose data acquisition reduced dynamic range specification. Electroencephalography (EEG) Industrial process control The specified operating temperature range is 40C to +105C, although the device is operational up to +125C. GENERAL DESCRIPTION 1 Note that throughout this data sheet, certain terms are used to The AD7771 is an 8-channel, simultaneous sampling analog-to- refer to either the multifunction pins or a range of pins. The digital converter (ADC). Eight full - ADCs are on-chip. The multifunction pins, such as DCLK0/SDO, are referred to either AD7771 provides an ultralow input current to allow direct sensor by the entire pin name or by a single function of the pin, for connection. Each input channel has a programmable gain stage example, DCLK0, when only that function is relevant. In the allowing gains of 1, 2, 4, and 8 to map lower amplitude sensor case of ranges of pins, AVSSx refers to the following pins: outputs into the full-scale ADC input range, maximizing the AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4. dynamic range of the signal chain. The AD7771 accepts a V REF 1 This product is protected by at least U.S. Patent No. 9,432,043. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20172018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com AD7771 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 - Output Data............................................................................. 54 Applications ....................................................................................... 1 ADC Conversion OutputHeader and Data ........................ 54 General Description ......................................................................... 1 Sample Rate Converter (SRC) (SPI Control Mode) .............. 55 Revision History ............................................................................... 3 Data Output Interface ................................................................ 57 Functional Block Diagram .............................................................. 4 Calculating the CRC Checksum .............................................. 61 Specifications ..................................................................................... 5 Register Summary .......................................................................... 62 DOUTx Timing Characterististics ............................................. 9 Register Details ............................................................................... 66 SPI Timing Characterististics ................................................... 10 Channel 0 Configuration Register ........................................... 66 Synchronization Pins and Reset Timing Characteristics ...... 11 Channel 1 Configuration Register ........................................... 66 SAR ADC Timing Characterististics ....................................... 12 Channel 2 Configuration Register ........................................... 67 GPIO SRC Update Timing Characterististics......................... 12 Channel 3 Configuration Register ........................................... 67 Absolute Maximum Ratings .......................................................... 13 Channel 4 Configuration Register ........................................... 68 Thermal Resistance .................................................................... 13 Channel 5 Configuration Register ........................................... 68 ESD Caution ................................................................................ 13 Channel 6 Configuration Register ........................................... 69 Pin Configuration and Function Descriptions ........................... 14 Channel 7 Configuration Register ........................................... 69 Typical Performance Characteristics ........................................... 17 Disable Clocks to ADC Channel Register .............................. 70 Terminology .................................................................................... 32 Channel 0 Sync Offset Register ................................................ 70 Theory of Operation ...................................................................... 34 Channel 1 Sync Offset Register ................................................ 70 Analog Inputs .............................................................................. 34 Channel 2 Sync Offset Register ................................................ 70 Transfer Function ....................................................................... 35 Channel 3 Sync Offset Register ................................................ 71 Core Signal Chain....................................................................... 36 Channel 4 Sync Offset Register ................................................ 71 Capacitive PGA ........................................................................... 36 Channel 5 Sync Offset Register ................................................ 71 Internal Reference and Reference Buffers ............................... 36 Channel 6 Sync Offset Register ................................................ 71 Integrated LDOs ......................................................................... 37 Channel 7 Sync Offset Register ................................................ 71 Clocking and Sampling .............................................................. 37 General User Configuration 1 Register ................................... 72 Digital Reset and Synchronization Pins .................................. 37 General User Configuration 2 Register ................................... 73 Digital Filtering ........................................................................... 38 General User Configuration 3 Register ................................... 74 Shutdown Mode .......................................................................... 38 Data Output Format Register ................................................... 74 Controlling the AD7771 ............................................................ 39 Main ADC Meter and Reference Mux Control Register ...... 75 Pin Control Mode ....................................................................... 39 Global Diagnostics Mux Register ............................................. 76 SPI Control .................................................................................. 42 GPIO Configuration Register ................................................... 76 Digital SPI .................................................................................... 45 GPIO Data Register.................................................................... 77 RMS Noise and Resolution............................................................ 48 Buffer Configuration 1 Register ............................................... 77 High Resolution Mode ............................................................... 48 Buffer Configuration 2 Register ............................................... 77 Low Power Mode ........................................................................ 49 Channel 0 Offset Upper Byte Register..................................... 78 Diagnostics and Monitoring ......................................................... 50 Channel 0 Offset Middle Byte Register ................................... 78 Self Diagnostics Error ................................................................ 50 Channel 0 Offset Lower Byte Register ..................................... 78 Monitoring Using the AD7771 SAR ADC (SPI Control Channel 0 Gain Upper Byte Register ....................................... 78 Mode) ........................................................................................... 51 Channel 0 Gain Middle Byte Register ..................................... 78 - ADC Diagnostics (SPI Control Mode) ............................ 53 Channel 0 Gain Lower Byte Register ....................................... 79 Rev. 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