16-Bit, 15 MSPS, Module Data Acquisition Solution Data Sheet ADAQ23875 FEATURES GENERAL DESCRIPTION The ADAQ23875 is a precision, high speed, Module data Integrated fully differential ADC driver with signal scaling acquisition solution that reduces the development cycle of a Wide input common-mode voltage range precision measurement systems by transferring the design High common-mode rejection burden of component selection, optimization, and layout from Single-ended to differential conversion the designer to the device. 2.048 V input range with 4.096 V REFBUF Critical passive components Using system-in-package (SIP) technology, the ADAQ23875 0.005% precision matched resistor array for FDA reduces end system component count by combining multiple 9 mm 9 mm, 0.80 mm pitch, 100-ball CSP BGA package common signal processing and conditioning blocks in a single 4 footprint reduction vs. discrete solution device, solving many design challenges. These blocks include a Low power, dynamic power scaling, power-down mode low noise, fully differential analog-to-digital converter (ADC) 143 mW typical at 15 MSPS driver (FDA), a stable reference buffer, and a high speed, 16-bit, Throughput: 15 MSPS, no pipeline delay 15 MSPS successive approximation register (SAR) ADC. INL: 0.6 LSB typical, 1 LSB maximum Using Analog Devices, Inc., iPassives technology, the SINAD: 89 dB typical at 1 kHz ADAQ23875 also incorporates crucial passive components THD: 115 dB at 1 kHz, 106 dB at 400 kHz with superior matching and drift characteristics to minimize Gain error: 0.005%FS typical temperature dependent error sources and to offer optimized Gain error drift: 1 ppm/C maximum performance (see Figure 1). The fast settling of the ADC driver On-board reference buffer with VCMO generation stage, with fully differential or single-ended to differential input Serial LVDS interface and no latency of the SAR ADC, provides a unique solution for Wide operating temperature range: 40C to +85C high channel count multiplexed signal chain architectures and APPLICATIONS control loop applications. ATE The small footprint, 9 mm 9 mm CSP BGA package enables Data acquisition smaller form factor instruments without sacrificing performance. Hardware in the Loop (HiL) Single, 5 V supply operation is possible while achieving optimum Power analyzers performance from the device. The ADAQ23875 features a serial Nondestructive test (acoustic emissions) low voltage differential signaling (LVDS) digital interface with Mass spectrometry one-lane or two-lane output modes, allowing the user to Travelling wave fault location optimize the interface data rate for each application. The Medical imaging and instruments specified operation of the Module is from 40C to +85C. Ultrasonic flow meters FUNCTIONAL BLOCK DIAGRAM EXAMPLE 1 EXAMPLE 2 EXAMPLE 3 VS+ REFIN VCMO REFBUF VDD 0.1F 0.1F 0.5 IN+ IN +1.024V +4V +4V +4V 15k 0.1F 2.048V 1.024V 2 REFERENCE 10F 0.1F VIO 0.2F 1.3pF 1. 1k 82pF IN+ IN 24. 9 550 CNV+, CNV +1.024V IN 0V 0V 0V DA+/DA, DB+/DB, VCMO FDA 16-BIT, 15MSPS ADC 1.024V IN+ DCO+, DCO 550 24. 9 82pF CLK+, CLK 1.3pF 1. 1k IN IN+ 0.1F +1.024V SERIAL LVDS 1V 1V 1V ADAQ23875 INTERFACE 1.024V PDB AMP VS GND PDB ADC Figure 1. ADAQ23875 Configured for Gain = 2, 2.048 V Differential Input Range Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 2020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. 25390-001ADAQ23875 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 17 Applications ...................................................................................... 1 Circuit Information ................................................................... 17 Functional Block Diagram .............................................................. 1 Transfer Function ...................................................................... 17 Revision History ............................................................................... 2 Applications Information ............................................................. 18 Specifications .................................................................................... 3 Typical Application Diagram ................................................... 18 Timing Specifications .................................................................. 5 Voltage Reference Input ............................................................ 19 Absolute Maximum Ratings ........................................................... 7 Common-Mode Output ............................................................ 19 Thermal Resistance ...................................................................... 7 Power Supply .............................................................................. 19 Electrostatic Discharge (ESD) Ratings ...................................... 7 Digital Interface .............................................................................. 20 ESD Caution.................................................................................. 7 PCB Layout ................................................................................. 22 Pin Configuration and Function Descriptions ............................ 8 Outline Dimensions ....................................................................... 23 Typical Performance Characteristics ........................................... 10 Ordering Guide .......................................................................... 23 Terminology .................................................................................... 15 REVISION HISTORY 11/2020Revision 0: Initial Version Rev. 0 Page 2 of 23