Four ADC, Two DAC Low Power Codec with Audio Processor Data Sheet ADAU1772 FEATURES Low power (15 mW for typical noise cancelling solution) 2 2 I C and SPI control interfaces, self-boot from I C EEPROM Programmable audio processing engine 7 MP pins supporting dual stereo digital microphone inputs, 192 kHz processing path stereo PDM output, mute, DSP bypass, push-button Biquad filters, limiters, volume controls, mixing volume controls, and parameter bank switching Low latency, 24-bit ADCs and DACs 102 dB SNR (signal through PGA and ADC APPLICATIONS with A-weighted filter) Noise cancelling handsets, headsets, and headphones 107 dB combined SNR (signal through DAC and headphone Bluetooth ANC handsets, headsets, and headphones with A-weighted filter) Personal navigation devices Serial port sample rates from 8 kHz to 192 kHz Digital still and video cameras 38 s analog-to-analog latency 4 single-ended analog inputsconfigurable as microphone GENERAL DESCRIPTION or line inputs The ADAU1772 is a codec with four inputs and two outputs that Dual stereo digital microphone inputs incorporates a digital processing engine to perform filtering, Stereo analog audio outputsingle-ended or differential, level control, signal level monitoring, and mixing. The path configurable as either line output or headphone driver from the analog input to the DSP core to the analog output is PLL supporting any input clock rate from 8 MHz to 27 MHz optimized for low latency and is ideal for noise cancelling headsets. Full-duplex, asynchronous sample rate converters (ASRCs) With the addition of just a few passive components, a crystal, Power supplies and an EEPROM for booting, the ADAU1772 provides a Analog and digital I/O of 1.8 V to 3.3 V complete headset solution. Digital signal processing (DSP) core of 1.1 V to 1.8 V FUNCTIONAL BLOCK DIAGRAM MICBIAS0 MICROPHONE POWER LDO BIAS GENERATORS ADAU1772 MICBIAS1 MANAGEMENT REGULATOR AIN0REF ADC SDATA1/CLKOUT/MP6 PGA CLOCK ADC AIN0 PLL XTALI/MCLKIN OSCILLATOR MODULATOR ADC XTALO DECIMATOR AIN1REF HPOUTLP/LOUTLP PGA DAC ADC AIN1 HPOUTLN/LOUTLN MODULATOR ADC DECIMATOR INPUT/OUTPUT SIGNAL STEREO PDM ROUTING MODULATOR DMIC0 1/MP4 DIGITAL MICROPHONE DMIC2 3/MP5 INPUTS HPOUTRP/LOUTRP DAC HPOUTRN/LOUTRN AIN2REF ADC PGA DECIMATOR DAC SDATA/MP0 ADC AIN2 SERIAL MODULATOR ADC SDATA0/PDMOUT/MP1 BIDIRECTIONAL INPUT/ ASRCS OUTPUT BCLK/MP2 PORT AIN3REF DSP CORE: LRCLK/MP3 ADC PGA BIQUAD FILTERS, DECIMATOR 2 ADC I C/SPI CONTROL AIN3 LIMITERS, MODULATOR INTERFACE AND SELF-BOOT VOLUME CONTROLS, MIXING CM Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com PD DVDD REG OUT AVDD DGND AVDD AGND AVDD AGND IOVDD AGND SELFBOOT ADDR0/SS ADDR1/MOSI SCL/SCLK SDA/MISO 10804-001ADAU1772 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Control Port .................................................................................... 40 2 Applications ....................................................................................... 1 I C Port ........................................................................................ 40 General Description ......................................................................... 1 SPI Port ........................................................................................ 43 Functional Block Diagram .............................................................. 1 Self-Boot ...................................................................................... 44 Revision History ............................................................................... 3 Multipurpose Pins .......................................................................... 45 Specif icat ions ..................................................................................... 4 Push-Button Volume Controls ................................................. 45 Analog Performance Specifications ........................................... 4 Limiter Compression Enable .................................................... 45 Crystal Amplifier Specifications ................................................. 7 Parameter Bank Switching ........................................................ 45 Digital Input/Output Specifications........................................... 8 Mute ............................................................................................. 45 Power Supply Specifications........................................................ 8 DSP Bypass Mode ...................................................................... 46 Typical Power Consumption ....................................................... 9 Serial Data Input/Output Ports .................................................... 47 Digital Filters ................................................................................. 9 Tristating Unused Channels...................................................... 47 Digital Timing Specifications ................................................... 10 Applications Information .............................................................. 50 Absolute Maximum Ratings .......................................................... 14 Power Supply Bypass Capacitors .............................................. 50 Thermal Resistance .................................................................... 14 Layout .......................................................................................... 50 ESD Caution ................................................................................ 14 Grounding ................................................................................... 50 Pin Configuration and Function Descriptions ........................... 15 Exposed Pad PCB Design ......................................................... 50 Typical Performance Characteristics ........................................... 17 Register Summary .......................................................................... 51 System Block Diagrams ................................................................. 28 Register Details ............................................................................... 53 Theory of Operation ...................................................................... 29 Clock Control Register .............................................................. 53 System Clocking and Power-Up ................................................... 30 PLL Denominator MSB Register .............................................. 54 Clock Initialization ..................................................................... 30 PLL Denominator LSB Register ............................................... 54 PLL ............................................................................................... 30 PLL Numerator MSB Register .................................................. 54 Clock Output ............................................................................... 31 PLL Numerator LSB Register .................................................... 55 Power Sequencing ...................................................................... 31 PLL Integer Setting Register ..................................................... 55 Signal Routing ................................................................................. 32 PLL Lock Flag Register .............................................................. 56 Input Signal Paths ........................................................................... 33 CLKOUT Setting Selection Register ........................................ 56 Analog Inputs .............................................................................. 33 Regulator Control Register ....................................................... 57 Digital Microphone Input ......................................................... 34 Core Control Register ................................................................ 58 Analog-to-Digital Converters ................................................... 34 Filter Engine and Limiter Control Register ............................ 59 Output Signal Paths ........................................................................ 35 DB Value Register 0 Read .......................................................... 60 Analog Outputs........................................................................... 35 DB Value Register 1 Read .......................................................... 60 Digital-to-Analog Converters ................................................... 35 DB Value Register 2 Read .......................................................... 61 PDM Output ............................................................................... 35 Core Channel 0/Core Channel 1 Input Select Register ......... 62 Asynchronous Sample Rate Converters .................................. 36 Core Channel 2/Core Channel 3 Input Select Register ......... 63 Signal Levels ................................................................................ 36 DAC Input Select Register ........................................................ 64 Signal Processing ............................................................................ 37 PDM Modulator Input Select Register .................................... 65 Instructions ................................................................................. 37 Serial Data Output 0/Serial Data Output 1 Input Select Register ........................................................................................ 66 Data Memory .............................................................................. 37 Parameters ................................................................................... 37 Rev. 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