Four-ADC, Two-DAC, Low Power Codec with Audio Processor Data Sheet ADAU1777 FEATURES APPLICATIONS Programmable audio processing engine Noise canceling handsets, headsets, and headphones Fast (up to 768 kHz) and slow processing paths Bluetooth active noise canceling (ANC) handsets, headsets, Biquad filters, limiters, volume controls, and mixing and headphones Low latency, 24-bit ADCs and DACs Personal navigation devices 102 dB SNR (through PGA and ADC with A weighted filter) Digital still and video cameras 108 dB combined SNR (through DAC and headphone with GENERAL DESCRIPTION A weighted filter) The ADAU1777 is a codec with four inputs and two outputs that Serial port sampling rate from 8 kHz to 192 kHz incorporates a digital processing engine to perform filtering, 5 s analog-to-analog latency level control, signal level monitoring, and mixing. The path 4 single-ended analog inputs, configurable as microphone from the analog input to the DSP core to the analog output is or line inputs optimized for low latency and is ideal for noise canceling headsets. Dual stereo digital microphone inputs With the addition of just a few passive components, a crystal, Stereo analog audio output, single-ended or differential, and an EEPROM for booting, the ADAU1777 provides a complete configurable as either line output or headphone driver headset solution. PLL supporting any input clock rate from 8 MHz to 27 MHz Full duplex, asynchronous sample rate converters (ASRCs) Note that throughout this data sheet, multifunction pins, such as Power supplies SCL/SCLK, are referred to either by the entire pin name or by a Analog and digital input/output of 1.8 V to 3.3 V single function of the pin, for example, SCLK, when only that Digital signal processing (DSP) core of 1.1 V to 1.8 V function is relevant. Low power 2 2 I C and SPI control interfaces, self boot from I C EEPROM 7 multipurpose (MPx) pins for digital controls and outputs FUNCTIONAL BLOCK DIAGRAM MICBIAS0 MICROPHONE POWER LDO BIAS GENERATORS ADAU1777 MICBIAS1 MANAGEMENT REGULATOR ADC SDATA1/CLKOUT/MP6 AIN0 PGA CLOCK PLL XTALI/MCLKIN ADC OSCILLATOR XTALO HPOUTLP/LOUTLP AIN1 PGA DAC ADC HPOUTLN/LOUTLN INPUT/OUTPUT SIGNAL STEREO PDM ROUTING DMIC0 1/MP4 MODULATOR DIGITAL MICROPHONE DMIC2 3/MP5 INPUTS HPOUTRP/LOUTRP DAC HPOUTRN/LOUTRN AIN2 PGA DAC SDATA/MP0 SERIAL ADC ADC SDATA0/PDMOUT/MP1 BIDIRECTIONAL INPUT/ ASRCS OUTPUT BCLK/MP2 PORT DSP CORE: LRCLK/MP3 AIN3 PGA BIQUAD FILTERS, 2 I C/SPI CONTROL LIMITERS, ADC INTERFACE AND SELF BOOT VOLUME CONTROLS, MIXING CM Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com PD DVDD DGND AGND REG OUT AGND AVDD AVDD AGND AVDD IOVDD SELFBOOT ADDR0/SS ADDR1/MOSI SCL/SCLK SDA/MISO 14796-001ADAU1777 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Burst Mode Communication .................................................... 35 2 Applications ....................................................................................... 1 I C Port ........................................................................................ 35 General Description ......................................................................... 1 SPI Port ........................................................................................ 38 Functional Block Diagram .............................................................. 1 Self Boot ....................................................................................... 39 Revision History ............................................................................... 3 Multipurpose Pins .......................................................................... 40 Specifications ..................................................................................... 4 Push-Button Volume Controls ................................................. 40 Analog Performance Specifications ........................................... 4 Limiter Compression Enable .................................................... 40 Crystal Amplifier Specifications ................................................. 8 Parameter Bank Switching ........................................................ 40 Digital Input/Output Specifications........................................... 8 Mute ............................................................................................. 40 Power Supply Specifications........................................................ 8 DSP Bypass Mode ...................................................................... 41 Typical Power Management Settings ......................................... 9 Serial Data Input/Output Ports .................................................... 42 Digital Filters Specifications ....................................................... 9 Tristating Unused Channels ..................................................... 42 Digital Timing Specifications ................................................... 10 Applications Information .............................................................. 45 Absolute Maximum Ratings .......................................................... 14 Power Supply Bypass Capacitors .............................................. 45 Thermal Resistance .................................................................... 14 Layout .......................................................................................... 45 ESD Caution ................................................................................ 14 Grounding ................................................................................... 45 Pin Configuration and Function Descriptions ........................... 15 PCB Stackup ................................................................................ 45 Typical Performance Characteristics ........................................... 17 Low Latency Register Settings ...................................................... 46 Theory of Operation ...................................................................... 24 Register Summary .......................................................................... 49 System Clocking and Power-Up ................................................... 25 Register Details ............................................................................... 52 Clock Initialization ..................................................................... 25 Clock Control Register .............................................................. 52 PLL................................................................................................ 25 PLL Denominator MSB Register .............................................. 53 Clock Output ............................................................................... 26 PLL Denominator LSB Register ............................................... 53 Power Sequencing ...................................................................... 26 PLL Numerator MSB Register .................................................. 53 Signal Routing ................................................................................. 27 PLL Numerator LSB Register .................................................... 54 Input Signal Paths ........................................................................... 28 PLL Integer Setting Register ..................................................... 54 Analog Inputs .............................................................................. 28 PLL Lock Flag Register .............................................................. 55 Digital Microphone Input ......................................................... 29 CLKOUT Setting Selection Register ........................................ 55 Analog-to-Digital Converters (ADCs) .................................... 29 Regulator Control Register ....................................................... 56 Output Signal Paths ........................................................................ 30 Core Control Register ................................................................ 56 Analog Outputs........................................................................... 30 Sleep on Program Address Count Register ............................. 57 Digital-to-Analog Converters (DACs) .................................... 30 Filter Engine and Limiter Control Register ............................ 59 PDM Output ............................................................................... 30 DB Value Register 0 Read .......................................................... 59 Asynchronous Sample Rate Converters .................................. 31 DB Value Register 1 Read .......................................................... 60 Signal Levels ................................................................................ 31 DB Value Register 2 Read .......................................................... 60 Signal Processing ............................................................................ 32 Core Channel 0/Core Channel 1 Input Select Register ......... 61 Instructions ................................................................................. 32 Core Channel 2/Core Channel 3 Input Select Register ......... 62 Data Memory .............................................................................. 32 DAC Input Select Register ........................................................ 63 Parameters ................................................................................... 32 PDM Modulator Input Select Register .................................... 64 Control Port..................................................................................... 35 Rev. 0 Page 2 of 108