Quad Analog-to-Digital Converter (ADC) Data Sheet ADAU1979 FEATURES GENERAL DESCRIPTION Four 4.5 V rms (typical) differential inputs The ADAU1979 incorporates four high performance, analog- On-chip phase-locked loop (PLL) for master clock to-digital converters (ADCs) with 4.5 V rms capable ac-coupled Low electromagnetic interference (EMI) design inputs. The ADCs use a multibit sigma-delta (-) architecture 109 dB (typical) analog-to-digital converter (ADC) dynamic 2 with continuous time front end for low EMI. An I C/serial range peripheral interface (SPI) control port is included that allows a Total harmonic distortion + noise (THD + N): 95 dB (typical) microcontroller to adjust volume and many other parameters. Selectable digital high-pass filter The ADAU1979 uses only a single 3.3 V supply. The device 24-bit stereo ADC with 8 kHz to 192 kHz sample rates internally generates the required digital DVDD supply. The low Digital volume control with autoramp function power architecture reduces the power consumption. The on-chip 2 I C/SPI controllable for flexibility PLL can derive the master clock from an external clock input or Software-controllable clickless mute frame clock (sample rate clock). When fed with the frame clock, Software power-down 2 it eliminates the need for a separate high frequency master Right justified, left justified, I S, and TDM modes clock in the system. The ADAU1979 is available in a 40-lead Master and slave operation modes LFCSP. 40-lead LFCSP Qualified for automotive applications Note that throughout this data sheet, multifunction pins, such as SCL/CCLK, are referred to either by the entire pin name or APPLICATIONS by a single function of the pin, for example, CCLK, when only Automotive audio systems that function is relevant. Active noise cancellation systems FUNCTIONAL BLOCK DIAGRAM 3.3V TO 1.8V DVDD REGULATOR ADAU1979 AVDDx AIN1 IOVDD ADC AIN1 AIN2 LRCLK ADC AIN2 BCLK AIN3 ADC AIN3 SDATAOUT1 AIN4 SDATAOUT2 ADC AIN4 AGNDx SCL/CCLK SDA/COUT AVDDx 2 I C/SPI ADDR1/CIN BG CONTROL PLL ADDR0/CLATCH REF PD/RST AGNDx AGNDx Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132021 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. AGND1 AGND2 AGND3 AGND4 AGND5 AGND6 DGND VREF MCLKIN AVDD1 AVDD3 PROGRAMMABLE GAIN AVDD2 PLL FILT DECIMATOR/HPF DC CALIBRATION SA MODE SERIAL AUDIO PORT 11408-001ADAU1979 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SPI Mode ..................................................................................... 24 Applications ....................................................................................... 1 Register Summary .......................................................................... 26 General Description ......................................................................... 1 Register Details ............................................................................... 27 Functional Block Diagram .............................................................. 1 Master Power and Soft Reset Register ..................................... 27 Revision History ............................................................................... 2 PLL Control Register ................................................................. 28 Specifications ..................................................................................... 3 Block Power Control and Serial Port Control Register ......... 29 Analog Performance Specifications ........................................... 3 Serial Port Control Register 1 ................................................... 30 Digital Input/Output Specifications........................................... 3 Serial Port Control Register 2 ................................................... 31 Power Supply Specifications........................................................ 4 Channel 1 and Channel 2 Mapping for Output Serial Ports Register ........................................................................................ 32 Digital Filter Specifications ......................................................... 4 Channel 3 and Channel 4 Mapping for Output Serial Ports Timing Specifications .................................................................. 5 Register ........................................................................................ 34 Absolute Maximum Ratings ............................................................ 7 Serial Output Drive Control and Overtemperature Protection Thermal Resistance ...................................................................... 7 Status Register ............................................................................. 35 ESD Caution .................................................................................. 7 Post ADC Gain Channel 1 Control Register .......................... 36 Pin Configuration and Function Descriptions ............................. 8 Post ADC Gain Channel 2 Control Register .......................... 37 Typical Performance Characteristics ........................................... 10 Post ADC Gain Channel 3 Control Register .......................... 37 Theory of Operation ...................................................................... 12 Post ADC Gain Channel 4 Control Register .......................... 38 Overview ...................................................................................... 12 High-Pass Filter and DC Offset Control Register and Master Power Supply and Voltage Reference ....................................... 12 Mute Register .............................................................................. 38 Power-On Reset Sequence ........................................................ 12 ADC Clipping Status Register .................................................. 39 PLL and Clock ............................................................................. 13 Digital DC High-Pass Filter and Calibration Register .......... 40 Analog Inputs .............................................................................. 14 Typical Application Circuit ........................................................... 41 ADC ............................................................................................. 16 Outline Dimensions ....................................................................... 42 ADC Summing Modes .............................................................. 16 Ordering Guide .......................................................................... 42 Serial Audio Data Output Ports, Data Format ....................... 17 Automotive Products ................................................................. 42 Control Ports ................................................................................... 21 2 I C Mode ...................................................................................... 21 REVISION HISTORY 4/2021Rev. 0 to Rev. A Changes to Table 6 ............................................................................ 7 Updated Outline Dimensions ....................................................... 42 11/2013Revision 0: Initial Version Rev. A Page 2 of 42