SPI Interface, Low C and Q , 15 V/+12 V, ON INJ 1.8 V Logic Control, 8:1/Dual 4:1 Mux Switches Data Sheet ADGS1208/ADGS1209 FEATURES FUNCTIONAL BLOCK DIAGRAMS SPI interface with error detection ADGS1208 Includes CRC, invalid read/write address, and SCLK count S1 error detection Supports burst mode and daisy-chain mode Industry standard SPI Mode 0 and SPI Mode 3 interface D compatible Round robin mode allows switching times that are comparable with a parallel interface S8 Four general-purpose digital outputs that can be used to GPO1 CNV control other devices GPO2 SPI GPO3 INTERFACE SDO <1 pC charge injection over full signal range GPO4 1 pF off capacitance SCLK SDI CS RESET/V V to V analog signal range SS DD L Fully specified at 15 V and +12 V Figure 1. ADGS1208 Functional Block Diagram 1.8 V logic compatibility with 2.7 V V 3.3 V L ADGS1209 24-lead LFCSP package S1A APPLICATIONS DA S4A Audio and video routing Automatic test equipment Data acquisition systems S1B Battery-powered systems DB S4B Sample-and-hold systems GPO1 Communication systems CNV GPO2 SPI INTERFACE SDO GPO3 GENERAL DESCRIPTION GPO4 The ADGS1208/ADGS1209 are analog multiplexers comprising SCLK SDI CS RESET/V L eight single channels and four differential channels, respectively. A Figure 2. ADGS1209 Functional Block Diagram serial peripheral interface (SPI) controls the switches. The SPI interface has robust error detection features, such as cyclic The ultralow on capacitance (C ) and exceptionally low charge ON redundancy check (CRC) error detection, invalid read/write injection (Q ) of these multiplexers make them ideal solutions INJ address detection, and SCLK count error detection. for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. It is possible to daisy-chain multiple ADGS1208/ADGS1209 devices together. Daisy-chain mode enables the configuration of PRODUCT HIGHLIGHTS multiple devices with a minimal amount of digital lines. The 1. SPI interface removes the need for parallel conversion, ADGS1208/ADGS1209 can also operate in burst mode to logic traces, and reduces GPIO channel count. decrease the time between SPI commands. 2. Daisy-chain mode removes additional logic traces when iCMOS construction ensures ultralow power dissipation, multiple devices are used. making the devices ideally suited for portable and battery- 3. CRC error detection, invalid read/write address detection, powered instruments. and SCLK count error detection ensure a robust digital interface. Each switch conducts equally well in both directions when on, 4. CRC and error detection capabilities allow the use of the and each switch has an input signal range that extends to the ADGS1208/ADGS1209 in safety critical systems. supplies. In the off condition, signal levels up to the supplies are blocked. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 16724-002 16724-001ADGS1208/ADGS1209 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Software Reset ............................................................................. 23 Applications ....................................................................................... 1 Daisy-Chain Mode ..................................................................... 23 General Description ......................................................................... 1 Power-On Reset .......................................................................... 24 Functional Block Diagrams ............................................................. 1 Round Robin Mode.................................................................... 25 Product Highlights ........................................................................... 1 General-Purpose Outputs ......................................................... 26 Revision History ............................................................................... 2 Applications Information .............................................................. 27 Specifications ..................................................................................... 3 Digital Input Buffers .................................................................. 27 15 V Dual Supply ....................................................................... 3 Settling Time ............................................................................... 27 12 V Single Supply ........................................................................ 5 Power Supply Rails ..................................................................... 27 Continuous Current per Channel, Sx or Dx ............................. 8 Power Supply Recommendations ............................................. 27 Timing Characteristics ................................................................ 9 Register Summaries ........................................................................ 28 Absolute Maximum Ratings .......................................................... 11 Register Details ............................................................................... 29 Thermal Resistance .................................................................... 11 Switch Data Register .................................................................. 29 ESD Caution ................................................................................ 11 Error Configuration Register .................................................... 30 Pin Configurations and Function Descriptions ......................... 12 Error Flags Register .................................................................... 30 Typical Performance Characteristics ........................................... 14 Burst Enable Register ................................................................. 31 Test Circuits ..................................................................................... 18 Round Robin Enable Register ................................................... 31 Terminology .................................................................................... 21 Round Robin Channel Configuration Register...................... 31 Theory of Operation ...................................................................... 22 CNV Edge Select Register ......................................................... 32 Address Mode ............................................................................. 22 Software Reset Register ............................................................. 32 Error Detection Features ........................................................... 22 Outline Dimensions ....................................................................... 33 Clearing the Error Flags Register ............................................. 23 Ordering Guide .......................................................................... 33 Burst Mode .................................................................................. 23 REVISION HISTORY 4/2018Revision 0: Initial Version Rev. 0 Page 2 of 33