SPI Interface, Quad SPST Switch, Low Q , INJ Low C , 15 V/+12 V, Mux Configurable ON Data Sheet ADGS1212 FEATURES FUNCTIONAL BLOCK DIAGRAM SPI interface with error detection ADGS1212 Includes CRC, invalid read/write address, and SCLK count S1 D1 error detection Supports burst mode and daisy-chain mode S2 D2 Industry-standard SPI Mode 0 and SPI Mode 3 compatible Guaranteed break-before-make switching allowing external S3 D3 wiring of switches to deliver multiplexer configurations S4 D4 V to V analog signal range SS DD Fully specified at 15 V and +12 V supply SPI SDO INTERFACE 4.5 V to 16.5 V dual-supply operation 5 V to 16.5 V single-supply operation Ultralow capacitance and leakage allows fast settling time SCLK SDI CS RESET/V L 1 pF typical off switch drain capacitance at 25C, 15 V Figure 1. 2.6 pF typical on switch capacitance at 25C, 15 V <1 pC typical charge injection at 25C 1.8 V logic compatibility with 2.7 V V 3.3 V L APPLICATIONS In the off condition, signal levels up to the supplies are blocked. Automated test equipment The ultralow capacitance and charge injection of these switches Data acquisition systems make them ideal solutions for data acquisition and sample-and- Battery-powered systems hold applications where low glitch and fast settling are required. Sample-and-hold systems Fast switching speed coupled with high signal bandwidth make Audio signal routing the device suitable for video signal switching. Video signal routing Multifunction pin names may be referenced by their relevant Communications systems function only. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADGS1212 contains four independent single-pole/single- 1. SPI interface removes the need for parallel conversion, throw (SPST) switches. A serial peripheral interface (SPI) logic traces, and reduces the general-purpose input/output controls the switches. The SPI interface has robust error detection (GPIO) channel count. features such as cyclic redundancy check (CRC) error detection, 2. Daisy-chain mode removes additional logic traces when invalid read/write address detection, and SCLK count error multiple devices are used. detection. 3. CRC error detection, invalid read/write address detection, It is possible to daisy-chain multiple ADGS1212 devices together. and SCLK count error detection ensure a robust digital Daisy-chain mode enables the configuration of multiple devices interface. with minimal digital lines. The ADGS1212 can also operate in 4. CRC and error detection capabilities allow the ADGS1212 burst mode to decrease the time between SPI commands. to be used in safety critical systems. iCMOS construction ensures ultralow power dissipation, making 5. Guaranteed break-before-make switching allows the the the device ideal for portable and battery-powered instruments. ADGS1212 to be used in multiplexer configurations with external wiring. Each switch conducts equally well in both directions when on, 6. The ADGS1212 1.8 V logic compatibility with 2.7 V VL and each switch has an input signal range that extends to the 3.3 V supplies. 7. Ultralow capacitance. 8. <1 pC charge injection. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 15936-001ADGS1212 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Error Detection Features ........................................................... 17 Applications ....................................................................................... 1 Clearing the Error Flags Register ............................................. 18 General Description ......................................................................... 1 Burst Mode .................................................................................. 18 Functional Block Diagram .............................................................. 1 Software Reset ............................................................................. 18 Product Highlights ........................................................................... 1 Daisy-Chain Mode ..................................................................... 18 Revision History ............................................................................... 2 Power-On Reset .......................................................................... 19 Specif icat ions ..................................................................................... 3 Applications Information .............................................................. 20 15 V Dual Supply ....................................................................... 3 Break-Before-Make Switching .................................................. 20 12 V Single Supply ........................................................................ 5 Power Supply Rails ..................................................................... 20 Continuous Current per Channel, Sx or Dx ............................. 6 Power Supply Recommendations ............................................. 20 Timing Characteristics ................................................................ 7 Register Summary .......................................................................... 21 Absolute Maximum Ratings ............................................................ 9 Register Details ............................................................................... 22 Thermal Resistance ...................................................................... 9 Switch Data Register .................................................................. 22 ESD Caution .................................................................................. 9 Error Configuration Register .................................................... 22 Pin Configuration and Function Descriptions ........................... 10 Error Flags Register .................................................................... 23 Typical Performance Characteristics ........................................... 11 Burst Enable Register ................................................................. 23 Test Circuits ..................................................................................... 14 Software Reset Register ............................................................. 23 Terminology .................................................................................... 16 Outline Dimensions ....................................................................... 24 Theory of Operation ...................................................................... 17 Ordering Guide .......................................................................... 24 Address Mode ............................................................................. 17 REVISION HISTORY 9/2017Revision 0: Initial Version Rev. 0 Page 2 of 24