SPI Interface, 1.5 R , 15 V/+12 V, ON Quad SPST Switch, Mux Configurable Data Sheet ADGS1412 FEATURES FUNCTIONAL BLOCK DIAGRAM SPI interface with error detection ADGS1412 Includes CRC, invalid read/write address, and SCLK count S1 D1 error detection S2 D2 Supports burst mode and daisy-chain mode Industry-standard SPI Mode 0 and Mode 3 interface compatible S3 D3 Guaranteed break-before-make switching allowing external wiring of switches to deliver multiplexer configurations S4 D4 1.5 typical on resistance at 25C SPI 0.3 typical on resistance flatness at 25C SDO INTERFACE 0.1 typical on resistance match between channels at 25C V to V analog signal range SS DD SCLK SDI CS RESET/V Fully specified at 15 V, 5 V, and +12 V L 1.8 V logic compatibility with 2.7 V V 3.3 V L Figure 1. 24-lead LFCSP APPLICATIONS Automated test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Video signal routing Communications systems Relay replacement GENERAL DESCRIPTION The ADGS1412 contains four independent single-pole/single- The on-resistance profile is flat over the full analog input range, throw (SPST) switches. A serial peripheral interface (SPI) which ensures good linearity and low distortion when switching controls the switches. The SPI interface has robust error detection audio signals. features such as cyclic redundancy check (CRC) error detection, PRODUCT HIGHLIGHTS invalid read/write address detection, and SCLK count error 1. SPI interface removes the need for parallel conversion, detection. logic traces and reduces general-purpose input/output It is possible to daisy-chain multiple ADGS1412 devices together. (GPIO) channel count. Daisy-chain mode enables the configuration of multiple devices 2. Daisy-chain mode removes additional logic traces when with a minimal amount of digital lines. The ADGS1412 can also multiple devices are used. operate in burst mode to decrease the time between SPI 3. CRC error detection, invalid read/write address detection, commands. and SCLK count error detection ensures a robust digital iCMOS construction ensures ultralow power dissipation, making interface. the device ideally suited for portable and battery-powered 4. CRC and error detection capabilities allow the use of the instruments. ADGS1412 in safety critical systems. 5. Guaranteed break-before-make switching allows the use of Each switch conducts equally well in both directions when on, the ADGS1412 in multiplexer configurations with external and each switch has an input signal range that extends to the wiring. supplies. In the off condition, signal levels up to the supplies 6. Minimum distortion. are blocked. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20162017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 14960-001ADGS1412 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Error Detection Features ........................................................... 20 Applications ....................................................................................... 1 Clearing the Error Flags Register ............................................. 21 Functional Block Diagrams ............................................................. 1 Burst Mode .................................................................................. 21 General Description ......................................................................... 1 Software Reset ............................................................................. 21 Product Highlights ........................................................................... 1 Daisy-Chain Mode ..................................................................... 21 Revision History ............................................................................... 2 Power-On Reset .......................................................................... 22 Specifications ..................................................................................... 3 Applications Information .............................................................. 23 15 V Dual Supply ....................................................................... 3 Break-Before-Make Switching .................................................. 23 5 V Dual Supply ......................................................................... 5 Digital Input Buffers .................................................................. 23 12 V Single Supply ........................................................................ 7 Power Supply Rails ..................................................................... 23 Continuous Current per Channel, Sx or Dx ............................. 9 Power Supply Recommendations ............................................. 23 Timing Characteristics ................................................................ 9 Register Summary .......................................................................... 24 Absolute Maximum Ratings .......................................................... 11 Register Details ............................................................................... 25 Thermal Resistance .................................................................... 11 Switch Data Register .................................................................. 25 ESD Caution ................................................................................ 11 Error Configuration Register .................................................... 25 Pin Configurations and Function Descriptions ......................... 12 Error Flags Register .................................................................... 26 Typical Performance Characteristics ........................................... 13 Burst Enable Register ................................................................. 26 Test Circuits ..................................................................................... 17 Software Reset Register ............................................................. 26 Terminology .................................................................................... 19 Outline Dimensions ....................................................................... 27 Theory of Operation ...................................................................... 20 Ordering Guide .......................................................................... 27 Address Mode ............................................................................. 20 REVISION HISTORY 8/2017Rev. A to Rev. B 3/2017Rev. 0 to Rev. A Changes to Product Title, Features Section, and Product Changes to Features Section and Product Highlights Section .... 1 Highlights Section ............................................................................ 1 Change to I Inactive Parameter, Table 1........................................ 4 L Changes to Table 1 ............................................................................ 3 Change to VDD = 15 V, VSS = 15 V (JA = 54C/W) Parameter, Changes to Table 2 ............................................................................ 5 Table 5 .................................................................................................. 7 Changes to Table 3 ............................................................................ 7 Change to Theory of Operation Section ..................................... 18 Changes to VL to GND Parameter and Digital Inputs Parameter, Updated Outline Dimensions Section ......................................... 25 Table 7 .............................................................................................. 11 Changes to Figure 17 ...................................................................... 14 10/2016Revision 0: Initial Version Added Figure 27 Renumbered Sequentially .............................. 16 Changes to Figure 30 ...................................................................... 17 Added Figure 35 .............................................................................. 17 Added Figure 36 .............................................................................. 18 Change to Theory of Operation Section ..................................... 20 Added Break-Before-Make Switching Section, Figure 45, and Digital Input Buffers Section......................................................... 23 Changes to Ordering Guide .......................................................... 27 Rev. B Page 2 of 27