SPI Interface, 1 R , 5 V, 12 V, 5 V, ON 3.3 V, Mux Configurable, Quad SPST Switch Data Sheet ADGS1612 FEATURES FUNCTIONAL BLOCK DIAGRAM SPI interface with error detection ADGS1612 Includes CRC, invalid read/write address, and SCLK count error detection S1 D1 Supports burst mode and daisy-chain mode Industry-standard SPI Mode 0 and SPI Mode 3 interface S2 D2 compatible S3 D3 Guaranteed break-before-make switching allowing external wiring of switches to deliver multiplexer configurations S4 D4 1 typical on resistance at 25C 0.23 typical on resistance flatness at 25C V to V analog signal range SS DD SPI SDO INTERFACE Fully specified at 5 V, 12 V, 5 V, and 3.3 V 3.3 V to 8 V dual-supply operation 3.3 V to 16 V single-supply operation SCLK SDI CS RESET/V L 1.8 V logic compatibility with 2.7 V V 3.3 V L Figure 1. 4 mm 4 mm, 24-lead LFCSP package APPLICATIONS Communication systems Medical systems Audio and video signal routing Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Relay replacements signals. The ADGS1612 exhibits break-before-make switching GENERAL DESCRIPTION action for use in multiplexer applications. Note that throughout The ADGS1612 contains four independent single-pole/single- RESET this data sheet, the multifunction pin, /VL, is referred to throw (SPST) switches. A serial peripheral interface (SPI) controls either by the entire pin name or by a single function of the pin, the switches. The SPI interface has robust error detection features, for example, V , when only that function is relevant. L including cyclic redundancy check (CRC) error detection, invalid read/write address detection, and serial clock (SCLK) PRODUCT HIGHLIGHTS count error detection. 1. The SPI interface removes the need for parallel conversion It is possible to daisy-chain multiple ADGS1612 devices together. and logic traces and reduces general-purpose input/output Daisy-chaining enables the configuration of multiple devices with a (GPIO) channel count. minimal amount of digital lines. The ADGS1612 can also operate 2. Daisy-chain mode removes additional logic traces when in burst mode to decrease the time between SPI commands. multiple devices are used. 3. CRC, invalid read/write address, and SCLK count error Each switch conducts equally well in both directions when on, and detection ensure a robust digital interface. each switch has an input signal range that extends to the supplies. 4. CRC error detection capabilities allow the use of the In the off condition, signal levels up to the supplies are blocked. ADGS1612 in safety critical systems. The ultralow on resistance (R ) of these switches make them ON 5. Guaranteed break-before-make switching allows the use of ideal solutions for data acquisition and gain switching the ADGS1612 in multiplexer configurations with external applications where low RON and low distortion are critical. The wiring. RON profile is very flat over the full analog input range, ensuring 6. Minimum distortion. excellent linearity and low distortion when switching audio Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 16054-001ADGS1612 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Address Mode ............................................................................. 22 Applications ....................................................................................... 1 Error Detection Features ........................................................... 22 Functional Block Diagram .............................................................. 1 Clearing the Error Flags Register ............................................. 23 General Description ......................................................................... 1 Burst Mode .................................................................................. 23 Product Highlights ........................................................................... 1 Software Reset ............................................................................. 23 Revision History ............................................................................... 2 Daisy-Chain Mode ..................................................................... 23 Specif icat ions ..................................................................................... 3 Power-On Reset .......................................................................... 24 5 V Dual Supply ......................................................................... 3 Applications Information .............................................................. 25 12 V Single Supply ........................................................................ 5 Break-Before-Make Switching .................................................. 25 5 V Single Supply .......................................................................... 7 Digital Input Buffers .................................................................. 25 3.3 V Single Supply ....................................................................... 9 Power Supply Rails ..................................................................... 25 Continuous Current per Channel, Sx or Dx ........................... 11 Register Summary .......................................................................... 26 Timing Characteristics .............................................................. 11 Register Details ............................................................................... 27 Absolute Maximum Ratings .......................................................... 13 Switch Data Register .................................................................. 27 Thermal Resistance .................................................................... 13 Error Configuration Register .................................................... 27 ESD Caution ................................................................................ 13 Error Flags Register .................................................................... 28 Pin Configuration and Function Descriptions ........................... 14 Burst Enable Register ................................................................. 28 Typical Performance Characteristics ........................................... 15 Software Reset Register ............................................................. 28 Test Circuits ..................................................................................... 19 Outline Dimensions ....................................................................... 29 Terminology .................................................................................... 21 Ordering Guide .......................................................................... 29 Theory of Operation ...................................................................... 22 REVISION HISTORY 1/2018Revision 0: Initial Version Rev. 0 Page 2 of 29