EVAL-ADIN2111EBZ Analog Devices

Data Sheet ADIN2111 Low Complexity, 2-Port Ethernet Switch with Integrated 10BASE-T1L PHYs FEATURES FUNCTIONAL BLOCK DIAGRAM 10BASE-T1L IEEE Standard 802.3cg-2019 compliant Supports 1.0 V p-p and 2.4 V p-p transmit levels Cable reach Up to 1700 meters with 1.0 V p-p transmit level Up to 1700 meters with 2.4 V p-p transmit level Low power consumption Single supply 1.0 V p-p: 90 mW typical Dual supply 1.0 V p-p: 77 mW typical Integrated switch with SPI 10 Mbps full duplex 16 MAC addresses supported for frame forwarding Supports OPEN Alliance 10BASE-T1x MACPHY SPI Figure 1. MDIO memory map accessible via SPI Supports high and low priority queues GENERAL DESCRIPTION Total buffer memory of 28 kB shared between ports and host The ADIN2111 is a low power, low complexity, two-Ethernet ports Autonegotiation capability switch with integrated 10BASE-T1L PHYs and one serial peripheral Managed or unmanaged configuration interface (SPI) port. The device is designed for industrial Ethernet Cut through or store and forward operation applications using low power constrained nodes and is compliant with the IEEE 802.3cg-2019 Ethernet standard for long reach IEEE 1588 time stamp capture on transmit and receive 10 Mbps single pair Ethernet (SPE). The switch (cut through or Diagnostics store and forward) supports various routing configurations between Frame generator and checker the two Ethernet ports and the SPI host port providing a flexible Multiple loopback modes solution for line, daisy-chain, or ring network topologies. IEEE test mode support The ADIN2111 supports cable reach of up to 1700 meters with ultra Port dedicated statistics counters low power consumption of 77 mW. The two PHY cores support Link and cable diagnostics the 1.0 V p-p operating mode and the 2.4 V p-p operating mode 25 MHz crystal or external clock input defined in the IEEE 802.3cg standard, and can operate from a Single or dual supply with 1.8 V or 3.3 V operation single power supply rail of 1.8 V or 3.3 V. The ADIN2111 can be used in unmanaged configurations where the device automatically Integrated power supply monitoring and POR forwards the traffic between the two Ethernet ports. Small package: 48-lead, 7 mm 7 mm LFCSP Temperature range The device integrates the switch, two Ethernet physical layer (PHY) cores with a media access control (MAC) interface and all the asso- Industrial: 40C to +85C ciated analog circuitry, and input and output clock buffering. The Extended: 40C to +105C device also includes internal buffer queues, the SPI and subsystem APPLICATIONS registers, as well as the control logic to manage the reset and clock control and hardware pin configuration. Building automation and fire safety The ADIN2111 has an integrated voltage supply monitoring circuit Factory automation and power-on reset (POR) circuitry to improve system level robust- Edge sensors and actuators ness. The 4-wire SPI for communication with the host can be Condition monitoring and machine connectivity configured to OPEN Alliance SPI or generic SPI. Both modes support optional data protection or cyclic redundancy check (CRC). Analog Devices is in the process of updating documentation to provide terminology and language that is culturally appropriate. This is a process with a wide scope and will be phased in as quickly as possible. Thank you for your patience. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliableas i. However, no responsibility is assumed by Analog DOCUMENT FEEDBACK Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and TECHNICAL SUPPORT registered trademarks are the property of their respective owners.Data Sheet ADIN2111 TABLE OF CONTENTS Features................................................................ 1 Unmanaged PHY Operation.............................23 Applications........................................................... 1 Managed PHY Operation................................. 23 Functional Block Diagram......................................1 On-Chip Diagnostics............................................27 General Description...............................................1 Loopback Modes..............................................27 Specifications........................................................ 3 Frame Generator and Checker........................ 28 Timing Characteristics........................................... 5 Frame Generator and Checker Link Test......... 29 Power-Up Timing................................................5 Test Modes.......................................................30 SPI......................................................................5 Applications Information...................................... 31 Absolute Maximum Ratings...................................7 System Level Power Management...................31 Thermal Resistance........................................... 7 Ethernet Daisy Chain, Line, and Ring Electrostatic Discharge (ESD) Ratings...............7 Network Topologies........................................32 ESD Caution.......................................................7 LED Circuit Examples...................................... 32 Pin Configuration and Function Descriptions........ 8 Component Recommendations........................33 Typical Performance Characteristics................... 11 Switch SPI........................................................... 35 Theory of Operation.............................................12 Overview.......................................................... 35 Overview.......................................................... 12 Generic SPI Protocol........................................35 Power Supply Domains....................................12 OPEN Alliance SPI Protocol.............................38 Analog Front-End............................................. 12 Frame Forwarding on Receive.........................45 Two Port Switch................................................12 Receive Priority Queues...................................45 Transmit Amplitude Configuration.................... 13 Statistics Counters........................................... 45 Master/Slave Configuration..............................13 Frame Receive and Transmit Errors................ 46 Autonegotiation................................................ 13 SPI Access to the PHY Registers.................... 46 MDI...................................................................16 Registers............................................................. 50 SPI....................................................................16 SPI Register Map ............................................ 50 Hardware Interrupt (INT).................................. 16 PHY Clause 22 Register Details ..................... 84 Reset Operations............................................. 17 PHY Clause 45 Register Details ..................... 87 Status LEDs..................................................... 18 PCB Layout Recommendations........................ 124 Power-Down Modes.........................................20 Land Pattern...................................................124 Hardware Configuration Pins...............................21 Component Placement and Routing.............. 124 Unmanaged Applications................................. 21 Crystal Placement and Routing......................124 Managed Applications......................................21 PCB Stack......................................................124 Hardware Configuration Pin Functions.............21 Outline Dimensions........................................... 125 Bringing Up 10BASE-T1L Links.......................... 23 Ordering Guide...............................................125 Overview.......................................................... 23 Evaluation Boards.......................................... 125 REVISION HISTORY 12/2021Revision 0: Initial Version analog.com Rev. 0 2 of 125