X-On Electronics has gained recognition as a prominent supplier of EVAL-ADM1060EBZ Power Management IC Development Tools across the USA, India, Europe, Australia, and various other global locations. EVAL-ADM1060EBZ Power Management IC Development Tools are a product manufactured by Analog Devices. We provide cost-effective solutions for Power Management IC Development Tools, ensuring timely deliveries around the world.

EVAL-ADM1060EBZ Analog Devices

EVAL-ADM1060EBZ electronic component of Analog Devices
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Part No.EVAL-ADM1060EBZ
Manufacturer: Analog Devices
Category: Power Management IC Development Tools
Description: Power Management IC Development Tools EVALUATION BOARD I.C.
Datasheet: EVAL-ADM1060EBZ Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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1: USD 392.4784 ea
Line Total: USD 392.48

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Communications System Supervisory/Sequencing Circuit ADM1060 FEATURES Faults detected on 7 independent supplies fault detection and sequencing/combinatorial logic for up to 1 high voltage supply (2 V to 14.4 V) seven independent supplies. The seven supply fault detectors 4 positive voltage only supplies (2 V to 6 V) consist of one high voltage detector (up to +14.4 V), two bipolar 2 positive/negative voltage supplies voltage detectors (up to +6 V or down to 6 V), and four posi- (+2 V to +6 V and 2 V to 6 V) Watchdog detector inputtimeout delay programmable tive low voltage detectors (up to +6 V). All of the detectors can from 200 ms to 12.8 sec be programmed to detect undervoltage, overvoltage, or out-of- 4 general-purpose logic inputs window (undervoltage or overvoltage) conditions. The inputs to Programmable logic blockcombinatorial and sequencing logic control of all inputs and outputs these supply fault detectors are via the VH (high voltage) pin, 9 programmable output drivers: VBn (positive or negative) pins, and VPn (positive only) pins. Open collector (external resistor required) Either the VH supply or one of the VPn supplies is used to Open collector with internal pull-up to VDD power the ADM1060 (whichever is highest). This ensures that Fast internal pull-up to V DD in the event of a supply failure, the ADM1060 is kept alive for as Open collector with internal pull-up to VPn long as possible, thus enabling a reliable fault flag to be asserted Fast internal pull-up to VPn Internally charge-pumped high drive (for use with and the system to be powered down in an ordered fashion. external N-channel FETsPDOs 1 to 4 only) EEPROM256 bytes of user EEPROM Other inputs to the ADM1060 include a watchdog detector Industry-standard 2-wire bus interface (SMBus) (WDI) and four general-purpose inputs (GPIn). The watchdog Guaranteed PDO low with VPn, VH = 1 V detector can be used to monitor a processor clock. If the clock does not toggle (transition from low to high or from high to APPLICATIONS low) within a programmable timeout period (up to 18 sec.), a Central office systems fail flag will assert. The four general-purpose inputs can be con- Servers figured as logic buffers or to detect positive/negative edges and Infrastructure network boards to generate a logic pulse or level from those edges. Thus, the High density, multivoltage system cards user can input control signals from other parts of the system GENERAL DESCRIPTION (e.g., RESET or POWER GOOD) to gate the sequencing of the supplies supervised by the ADM1060. The ADM1060 is a programmable supervisory/sequencing device that offers a single chip solution for multiple power The ADM1060 features nine programmable driver outputs supply fault detection and sequencing in communications (PDOs). All nine outputs can be configured to be logic outputs, systems. which can provide multiple functions for the end user such as RESET generation, POWER GOOD status, enabling of LDOs, In central offices, servers, and other infrastructure systems, a and watchdog timeout assertion. PDOs 1 to 4 have the added common backplane dc supply is reduced to multiple board sup- feature of being able to provide an internally charge-pumped plies using dc-to-dc converters. These multiple supplies are used high voltage for use as the gate drive of an external N-channel to power different sections of the board, such as 3.3 V logic FET that could be placed in the path of one of the supplies circuits, 5 V logic circuits, DSP core, and DSP I/O circuits. There being supervised. is usually a requirement that certain sections power up before others for example, a DSP core may need to power up before (continued on Page 3) the DSP I/O, or vice versa, to avoid damage, miscommunication, . or latch-up. The ADM1060 facilitates this, providing supply Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 2003 Analog Devices, Inc. All rights reserved. ADM1060 TABLE OF CONTENTS General Description ......................................................................... 3 PROGRAMMABLE DRIVER OUTPUTS ............................. 33 Specifications..................................................................................... 5 Status/Faults .................................................................................... 35 Absolute Maximum Ratings............................................................ 7 FAULT REGISTERS................................................................... 38 Typical Performance Characteristics ............................................. 8 MASK REGISTERS.................................................................... 39 Inputs................................................................................................ 11 Programming .................................................................................. 40 SFD REGISTER NAMES........................................................... 14 WRITE OPERATIONS ............................................................. 44 SFD Register Bit Maps ............................................................... 15 READ OPERATIONS................................................................ 45 Programming .................................................................................. 21 Pin Configuration and Functional Descriptions........................ 49 Logic ................................................................................................. 22 Outline Dimensions ....................................................................... 50 PLBA REGISTER BIT MAPS ................................................... 28 Ordering Guide .......................................................................... 50 Outputs ............................................................................................ 33 REVISION HISTORY 12/03Data sheet changed from Rev. A to Rev. B Changes to Specifications.............................................................................5 Changes to Outputs section............................................................33 Updated Outline Dimensions.........................................................50 5/03Data sheet changed from Rev. 0 to Rev. A. Changes to Features.......................................................................... 1 Changes to Specifications ................................................................ 5 Changes to Figure 1.......................................................................... 4 Changes to Absolute Maximum Ratings ....................................... 7 Changes to Figures 2, 8, 1516..................................................810 Changes to Figure 17...................................................................... 11 Changes to Programmable Supply Fault Detectors section...... 11 Changes to Figure 18...................................................................... 12 Changes to Figure 19...................................................................... 13 Change to Table 9 ........................................................................... 15 Change to Table 14 ......................................................................... 16 Change to Table 19 ......................................................................... 17 Changes to Programmable Driver Outputs section................... 33 Change to Table 40 ......................................................................... 34 Changes to Figure 2526 ............................................................... 43 Changes to Figure 37...................................................................... 47 Changes to Table 58........................................................................ 49 Changes to Ordering Guide section............................................. 50 Revision 0: Initial Version Rev. B Page 2 of 52

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