AN-744 APPLICATION NOTE One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 Tel: 781/329-4700 Fax: 781/326-8703 www.analog.com ADuC7026 Evaluation Board Reference Guide by Aude Richard TABLE OF CONTENTS hand side and a digital plane on the right-hand side of Evaluation Board Overview.......................................... 1 the board. The regulated 3.3 V power supply is routed Evaluation Board Features........................................... 1 directly to the digital section and is lfi tered before being DIP Switch Link Options............................................... 2 routed into the analog section of the board. External Connectors.................................................... 3 FEATURES External Memory Interface.......................................... 5 Power Supply Potentiometer Demonstration Circuit......................... 6 The user should connect the 9 V power supply via the Schematic.................................................................... 7 2.1 mm input power socket (J5). The input connector Parts List ..................................................................... 9 is configured as CENTER NEGATIVE, i.e., GND on the OVERVIEW center pin and +9 V on the outer shield. The ADuC7026 evaluation board has the following This 9 V supply is regulated via a linear voltage regulator features: (U5). The 3.3 V regulator output is used to drive the digital 2-Layer PCB (4 5 form factor) side of the board directly. The 3.3 V supply is also filtered and then used to supply the analog side of the board. 9 V power supply regulated to 3.3 V on board When on, the red LED (D3) indicates that a valid 3.3 V 4-pin UART header to connect to RS-232 interface supply is being driven from the regulator circuit. All cable active components are decoupled with 0.1 F at device 20-pin standard JTAG connector to connect to ULINK supply pins to ground. emulator RS-232 Interface Demonstration circuit The ADuC7026 (U1) P1.1 and P1.0 lines are connected to 32.768 kHz watch crystal to drive the PLL clock the RS-232 interface cable via connector (J1). The interface cable generates the required level shifting to allow direct ADR291 2.5 V external reference chip connection to a PC serial port. Ensure that the cable Reset/Download/IRQ0 push-buttons supplied is connected to the board correctly, i.e., DVDD is Power indicator/general-purpose LEDs connected to DVDD and DGND is connected to DGND. Access to all ADC inputs and DAC output from external Emulation Interface header. All device ports are brought out to external Nonintrusive emulation and download are possible on the header pins. ADuC7026 via JTAG by connecting the ULINK emulator to the J4 connector. Surface-mount and through hole general-purpose prototype area Crystal Circuit The board is fitted with a 32.768 kHz crystal, from which External memory and latch footprint the on-chip PLL circuit can generate a 45 MHz clock. Notes External Reference (ADR291) 1. This document refers to the MicroConverter ADuC7026 The external 2.5 V reference chip (U2) has two functions. Eval Board, Rev. A1. It is provided on the evaluation board to demonstrate the 2. All references in this document to physical orientation external reference option of the ADuC7026, but its main of components on the board are made with respect to purpose is to generate the V voltage of the differential OCM a component side view of the board with the prototype amplifier, if required. area appearing in the bottom of the board. Reset/Download/IRQ0 Push-buttons 3. The board is laid out to minimize coupling between the A RESET push-button is provided to allow the user to analog and digital sections of the board. To this end, the manually reset the part. When inserted, the RESET pin ground plane is split with the analog section on the left- of the ADuC7026 will be pulled to DGND. Because the REV. 0AN-744 AN-744 RESET pin on the ADuC7026 is Schmitt-triggered inter- External Memory and Latch Footprint nally there is no need to use an external Schmitt trigger Footprint for a 32 kB 16 static RAM (CY7C1020CV33) on this pin. and 16-bit latch is also on board. See External Memory Interface section. When inserted the IRQ0 push-button switch drives P0.4/IRQ0 high. This can be used to initiate an external DIP SWITCH LINK OPTIONS interrupt 0. S1-1 VREF To enter serial download mode the user must pull the Function: Connects the output of the 2.5 V external refer- P0.0/BM pin low while reset is toggled. On the evalua- ence (ADR291) to the VREF pin (Pin 55) of the tion board, serial download mode can be easily initiated ADuC7026. by holding down the serial download push-button (S2) Use: Slide S1-1 to the on position to connect the while inserting and releasing the reset button (S3) as external reference to the ADuC7026. illustrated in Figure 1. Slide S1-1 to the off position to use the internal 2.5 V reference or a different external reference on VREF pin of J3 header. S1-2 VOCM Function: Connects 1.67 V to the V pin of the AD8132. OCM No extra dc voltage is required on the board to use the ADC in differential mode. Use: Slide S1-2 to the on position to connect V OCM of the differential amplifier to 1.67 V, divided output of the ADR291 reference. Figure 1. Entering Serial Download Mode Slide S1-2 to the off position to use a different on the Evaluation Board voltage for V by connecting a dc voltage to OCM Power Indicator/General-Purpose LEDs the V pin of J3 header. Note that V value OCM OCM A red power LED (D3) is used to indicate that a sufficient is dependent on reference value as shown in supply is available on the board. A general-purpose LED Table 1. (D2) is directly connected to P4.2 of the ADuC7026. When Table 1. V Range P4.2 is cleared the LED will be turned on, and when P4.2 OCM is set, the LED will be turned off. V V min V max REF OCM OCM Analog I/O Connections 2.5 V 1.25 V 2.05 V All analog I/O are brought out on header J3. 2.048 V 1.024 V 2.276 V ADC0 and ADC1 are buffered using an AD8606 to evaluate 1.25 V 0.75 V 2.55 V single-ended and pseudo differential mode. A potentiometer can be connected to ADC0 buffered. S1-3 POT Function: Connects the potentiometer output to ADC0. ADC3 and ADC4 can be buffered with a single-ended to This input is buffered by an AD8606. This is differential op amp on board, the AD8132, used to evalu- for demonstration purposes. ate the ADC in fully differential mode. Use: Slide S1-3 to the on position to connect the ADC2 and ADC5 to ADC11 are not buffered. Be sure to potentiometer to the op amp of ADC0 input follow the data sheet recommendation when connecting channel. signals to these inputs. Slide S1-3 to the off position to use ADC0 DAC1 can be used to control the brightness of the green input on J3 header. LED D1, when connected via the S1 switch. S1-4 ADC3 General-Purpose Prototype Area Function: Brings out ADC3 (Pin 64) on J3 header. General-purpose prototype areas are provided at the bottom of the evaluation board for adding external Use: Slide S1-6 to the on position to connect components as required in the users application. As can directly ADC3 of J3 header to ADC3 pin be seen from the layout AV , AGND, V , and DGND DD DDIO (Pin 64) of the ADuC7026. tracks are provided in this prototype area. Slide S1-6 to the off position to disconnect ADC3 of J3 header from ADC3 pin (Pin 64) of the ADuC7026. 2 REV. 0 REV. 0 3