Low Power, Precision Analog Microcontroller, Dual Sigma-Delta ADCs, Flash/EE, ARM7TDMI Data Sheet ADuC7060/ADuC7061 FEATURES Packages and temperature range Fully specified for 40C to +125C operation Analog input/output 32-lead LFCSP (5 mm 5 mm) Dual (24-bit) ADCs 48-lead LFCSP and LQFP Single-ended and differential inputs Derivatives Programmable ADC output rate (4 Hz to 8 kHz) 32-lead LFCSP (ADuC7061) Programmable digital filters 48-lead LQFP and 48-lead LFCSP (ADuC7060) Built-in system calibration Low power operation mode APPLICATIONS Primary (24-bit) ADC channel Industrial automation and process control 2 differential pairs or 4 single-ended channels Intelligent, precision sensing systems, 4 mA to 20 mA PGA (1 to 512) input stage loop-based smart sensors Selectable input range: 2.34 mV to 1.2 V 30 nV rms noise GENERAL DESCRIPTION Auxiliary (24-bit) ADC: 4 differential pairs or 7 single- The ADuC7060/ADuC7061 series are fully integrated, 8 kSPS, ended channels 24-bit data acquisition systems incorporating high performance On-chip precision reference (10 ppm/C) multichannel sigma-delta (-) analog-to-digital converters Programmable sensor excitation current sources (ADCs), 16-bit/ 32-bit ARM7TDMI MCU, and Flash/EE memory 200 A to 2 mA current source range on a single chip. Single 14-bit voltage output DAC The ADCs consist of a primary ADC with two differential pairs or Microcontroller four single-ended channels and an auxiliary ADC with up to seven ARM7TDMI core, 16-/32-bit RISC architecture channels. The ADCs operate in single-ended or differential input JTAG port supports code download and debug mode. A single-channel buffered voltage output DAC is available Multiple clocking options on chip. The DAC output range is programmable to one of four Memory voltage ranges. 32 kB (16 kB 16) Flash/EE memory, including 2 kB kernel 4 kB (1 kB 32) SRAM The devices operate from an on-chip oscillator and a PLL gene- Tools rating an internal high frequency clock up to 10.24 MHz. The In-circuit download, JTAG based debug microcontroller core is an ARM7TDMI, 16-bit/32-bit RISC Low cost, QuickStart development system machine offering up to 10 MIPS peak performance 4 kB of SRAM Communications interfaces and 32 kB of nonvolatile Flash/EE memory are provided on chip. SPI interface (5 Mbps) The ARM7TDMI core views all memory and registers as a single 4-byte receive and transmit FIFOs linear array. 2 UART serial I/O and I C (master/slave) The ADuC7060/ADuC7061 contains four timers. Timer1 is a On-chip peripherals wake-up timer with the ability to bring the part out of power saving 4 general-purpose (capture) timers including mode. Timer2 is configurable as a watchdog timer. A 16-bit PWM Wake-up timer with six output channels is also provided. The ADuC7060/ Watchdog timer ADuC7061 contains an advanced interrupt controller. The Vectored interrupt controller for FIQ and IRQ vectored interrupt controller (VIC) allows every interrupt to be 8 priority levels for each interrupt type assigned a priority level. It also supports nested interrupts to a Interrupt on edge or level external pin inputs maximum level of eight per IRQ and FIQ. When IRQ and FIQ 16-bit, 6-channel PWM interrupt sources are combined, a total of 16 nested interrupt levels General-purpose inputs/outputs is supported. On-chip factory firmware supports in-circuit serial Up to 14 GPIO pins that are fully 3.3 V compliant download via the UART serial interface ports and nonintrusive Power emulation via the JTAG interface. The parts operate from 2.375 V AVDD/DVDD specified for 2.5 V (5%) to 2.625 V over an industrial temperature range of 40C to Active mode: 2.74 mA ( 640 kHz, ADC0 active) +125C. 10 mA ( 10.24 MHz, both ADCs active) Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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ADuC7060/ADuC7061 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 MMR Interface ........................................................................... 57 Applications ....................................................................................... 1 Using the DAC ............................................................................ 58 General Description ......................................................................... 1 Nonvolatile Flash/EE Memory ..................................................... 59 Revision History ............................................................................... 3 Flash/EE Memory Reliability .................................................... 59 Functional Block Diagram .............................................................. 5 Programming .............................................................................. 59 Specifications ..................................................................................... 6 Processor Reference Peripherals ................................................... 60 Electrical Specifications ............................................................... 6 Interrupt System ......................................................................... 60 Timing Specifications ................................................................ 11 IRQ ............................................................................................... 60 Absolute Maximum Ratings .......................................................... 15 Fast Interrupt Request (FIQ) .................................................... 61 ESD Caution ................................................................................ 15 Programmed Interrupts............................................................. 62 Pin Configurations and Function Descriptions ......................... 16 Vectored Interrupt Controller (VIC) ....................................... 62 Terminology .................................................................................... 21 VIC MMRs .................................................................................. 62 Overview of the ARM7TDMI Core ............................................. 22 Timers .............................................................................................. 67 Thumb Mode (T) ........................................................................ 22 HR:MIN:SEC: 1/128 Format .................................................... 67 Multiplier (M) ............................................................................. 22 Timer0.......................................................................................... 68 EmbeddedICE (I) ....................................................................... 22 Timer1 or Wake-Up Timer ....................................................... 70 ARM Registers ............................................................................ 22 Timer2 or Watchdog Timer ...................................................... 72 Interrupt Latency ........................................................................ 23 Timer3.......................................................................................... 74 Memory Organization ............................................................... 23 Pulse-Width Modulator ................................................................. 76 Flash/EE Control Interface ........................................................ 24 Pulse-Width Modulator General Overview ........................... 76 Memory Mapped Registers ....................................................... 28 UART Serial Interface .................................................................... 81 Complete MMR Listing ............................................................. 29 Baud Rate Generation ................................................................ 81 Reset ............................................................................................. 34 UART Register Definitions ....................................................... 81 2 Oscillator, PLL, and Power Control ............................................. 35 I C ..................................................................................................... 87 2 Clocking System ......................................................................... 35 Configuring External Pins for I C Functionality ................... 87 Power Control System ................................................................ 35 Serial Clock Generation ............................................................ 88 2 ADC Circuit Information .............................................................. 39 I C Bus Addresses ....................................................................... 88 2 Reference Sources ....................................................................... 40 I C Registers ................................................................................ 88 Diagnostic Current Sources ...................................................... 40 Serial Peripheral Interface ............................................................. 97 Sinc3 Filter ................................................................................... 41 MISO (Master In, Slave Out) Pin ............................................. 97 ADC Chopping ........................................................................... 41 MOSI (Master Out, Slave In) Pin ............................................. 97 Programmable Gain Amplifier ................................................. 41 SCLK (Serial Clock I/O) Pin ..................................................... 97 E Excitation Sources ...................................................................... 41 Slave Select (P0.0/SS) Input Pin ............................................... 97 ADC Low Power Mode .............................................................. 41 Configuring External Pins for SPI Functionality ................... 97 ADC Comparator and Accumulator ....................................... 42 SPI Registers ................................................................................ 98 Temperature Sensor ................................................................... 42 General-Purpose I/O ................................................................... 102 ADC MMR Interface ................................................................. 42 GPxCON Registers................................................................... 102 Example Application Circuits ................................................... 55 GPxDAT Registers ................................................................... 103 DAC Peripherals ............................................................................. 57 GPxSET Registers ..................................................................... 103 DAC .............................................................................................. 57 GPxCLR Registers .................................................................... 103 Rev. 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