Precision Analog Microcontroller, 12-Bit Analog Input/Output, ARM7TDMI MCU Data Sheet ADuC7120/ADuC7121 FEATURES Memory 126 kB Flash/EE memory, 8 kB SRAM Analog input/output In-circuit download, JTAG-based debug Multiple channel, 12-bit, 1 MSPS ADC Software triggered in-circuit reprogrammability 2 differential pairs with input PGA On-chip peripherals General-purpose inputs (differential or single-ended) 2 UART, 2 I C and SPI serial I/O ADuC7120: 11 channels 32-pin GPIO port ADuC7121: 7 channels 4 general-purpose timers Fully differential and single-ended modes Wake-up timers and WDT 0 V to V analog input voltage range (single-ended mode) REF Power supply monitor 5 low noise IDACs IDAC monitor 250 mA, 200 mA, 45 mA, 80 mA, 20 mA Temperature monitor 12-bit voltage output DACs Vectored interrupt controller for FIQ and IRQ ADuC7120: 12 channels 8 priority levels for each interrupt type ADuC7121: 4 channels Interrupt on edge or level external pin inputs 4 12-bit voltage output DACs Power On-chip voltage reference Specified for 3 V operation On-chip temperature sensor Normal mode: 11 mA at 5.22 MHz, 30 mA at 41.78 MHz Microcontroller Packages and temperature range ARM7TDMI core, 16-bit/32-bit RISC architecture 7 mm 7 mm 108-ball CSP BGA JTAG port supports code download and debug Fully specified for 40C to +105C operation Clocking options Tools Trimmed on-chip oscillator (3%) Low cost QuickStart development system External watch crystal Full third party support External clock source up to 41.78 MHz 41.78 MHz PLL with programmable divider APPLICATIONS Optical modulestunable laser FUNCTIONAL BLOCK DIAGRAM AVDD 3.3V AGND IDAC0 IDAC1 IDAC2 IDAC3 IDAC4 BUF DAC0 DAC ADuC7120: 12 CHANNELS ADuC7121: 4 CHANNELS DAC BUF DAC11 PADC0N PGA ADuC7120/ PADC0P ADuC7121 PLA PADC1N PGA PADC1P OSC PLL POR PWM 1MSPS ADC0 WAKE-UP 3 GP 8kB SRAM 12-BIT IOVDD (2k 32-BIT) TIMER TIMERS ADC1 LDO SAR ADC IOGND 126kB WDT FLASH ARM7 XTALI (63k ADC9 TDMI UART VIC XTALO 16-BIT) ADC10/AINCM RST GPIO 2 TEMPERATURE TDO JTAG SPI I C 2 CONTROL SENSOR TDI TCK TMS INTERNAL BUF REFERENCE TRST V 1.2 V 2.5 REF REF P0.0 TO P0.7 P1.0 TO P1.7 P2.0 TO P2.7 P3.0 TO P3.7 Figure 1. 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I DAC I DAC I DAC I DAC I DAC 09492-001ADuC7120/ADuC7121 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Other Analog Peripherals .............................................................. 46 Applications ....................................................................................... 1 DACs ............................................................................................ 46 Functional Block Diagram .............................................................. 1 Low Dropout (LDO) Regulator ................................................ 49 Revision History ............................................................................... 3 Current Output DACs (IDAC) ................................................. 50 General Description ......................................................................... 4 IDAC MMRs ............................................................................... 51 Specifications ..................................................................................... 5 Oscillator and PLLPower Control ........................................ 52 Timing Specifications ................................................................ 10 Digital Peripherals .......................................................................... 55 Absolute Maximum Ratings .......................................................... 15 Pulse-Width Modulator (PWM) Overview ............................ 55 Thermal Resistance .................................................................... 15 PWM Convert Start Control .................................................... 57 ESD Caution ................................................................................ 15 General-Purpose Input/Output .................................................... 58 Pin Configurations and Function Descriptions ......................... 16 UART Serial Interface .................................................................... 62 Terminology .................................................................................... 24 Baud Rate Generation ................................................................ 62 ADC Specifications .................................................................... 24 UART Register Definition ......................................................... 62 2 DAC Specifications..................................................................... 24 I C Peripherals ................................................................................ 66 Overview of the ARM7TDMI Core ............................................. 25 Serial Clock Generation ............................................................ 66 2 Thumb (T) Mode ........................................................................ 25 I C Bus Addresses ....................................................................... 66 2 Long Multiply (M) ...................................................................... 25 I C Registers ................................................................................ 67 2 EmbeddedICE (I) ....................................................................... 25 I C Common Registers .............................................................. 74 Exceptions ................................................................................... 25 Serial Peripheral Interface ............................................................. 75 ARM Registers ............................................................................ 26 SPI Master In, Slave Out (MISO) Pin ...................................... 75 Interrupt Latency ........................................................................ 26 SPI Master Out, Slave In (MOSI) Pin ...................................... 75 Memory Organization ................................................................... 27 Serial Clock Input/Output (SPICLK) Pin ............................... 75 Memory Access ........................................................................... 27 SPI Chip Select Input Pin .......................................................... 75 Flash/EE Memory ....................................................................... 27 Configuring External Pins for SPI Functionality ................... 75 SRAM ........................................................................................... 27 SPI Registers ................................................................................ 75 Memory Mapped Registers (MMR)......................................... 27 Programmable Logic Array (PLA) ............................................... 78 Complete MMR Listing ............................................................. 28 PLA MMRs Interface ................................................................. 79 ADC Circuit Overview .................................................................. 31 Interrupt System ............................................................................. 82 ADC Transfer Function ............................................................. 31 Normal Interrupt Request (IRQ) ............................................. 82 Temperature Sensor ................................................................... 33 Fast Interrupt Request (FIQ) .................................................... 83 Converter Operation .................................................................. 36 External Interrupts (IRQ0 to IRQ5) ........................................ 88 Driving the Analog Inputs ........................................................ 37 Timers .............................................................................................. 89 Band Gap Reference ................................................................... 38 Hour: Minute: Second: 1/128 Format ...................................... 89 Power Supply Monitor (PSM) ................................................... 39 Timer0Lifetime Timer ........................................................... 89 Nonvolatile Flash/EE Memory ..................................................... 40 Timer1General-Purpose Timer ........................................... 91 Flash/EE Memory Overview ..................................................... 40 Timer2Wake-Up Timer ......................................................... 93 Flash/EE Memory Security ....................................................... 41 Timer3Watchdog Timer ........................................................ 94 Flash/EE Control Interface ........................................................ 41 Timer4General-Purpose Timer ........................................... 97 Execution Time from SRAM and Flash/EE ............................ 44 Hardware Design Considerations ................................................ 99 Reset and Remap ........................................................................ 44 Power Supplies ............................................................................ 99 Rev. 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