MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62 kB Flash MCU Data Sheet ADuC841/ADuC842/ADuC843 FEATURES FUNCTIONAL BLOCK DIAGRAM Pin compatible upgrade of ADuC812/ADuC831/ADuC832 12-BIT 1 ADuC841/ADuC842/ADuC843 DAC Increased performance BUF DAC Single-cycle 20 MIPS 8052 core 12-BIT High speed 420 kSPS 12-bit ADC 1 DAC BUF DAC ADC0 Increased memory ADC1 T/H 12-BIT ADC Up to 62 kBytes on-chip Flash/EE program memory 16-BIT MUX - DAC 4 kBytes on-chip Flash/EE data memory ADC5 ADC6 16-BIT In-circuit reprogrammable PWM0 HARDWARE - DAC ADC7 CALIBRATON MUX Flash/EE, 100 year retention, 100 kCycle endurance 16-BIT 2304 bytes on-chip data RAM PWM1 TEMP PWM SENSOR Smaller package 16-BIT 8 mm 8 mm chip scale package PWM 52-lead PQFPpin-compatible upgrade 20 MIPS 8052 BASED MCU WITH ADDITIONAL PERIPHERALS Analog I/O 62 kBYTES FLASH/EE PROGRAM MEMORY 2 PLL 8-channel, 420 kSPS high accuracy, 12-bit ADC 4 kBYTES FLASH/EE DATA MEMORY 2304 BYTES USER RAM On-chip, 15 ppm/C voltage reference 3 16 BIT TIMERS POWER SUPPLY MON 1 REAL TIME CLOCK WATCHDOG TIMER INTERNAL DMA controller, high speed ADC-to-RAM capture BAND GAP OSC 2 1 4 PARALLEL UART, I C, AND SPI VREF Two 12-bit voltage output DACs PORTS SERIAL I/O Dual output PWM - DACs C XTAL1 XTAL2 REF On-chip temperature monitor function Figure 1. 8052 based core GENERAL DESCRIPTION 8051 compatible instruction set (20 MHz max) 1 High performance single-cycle core The ADuC841/ADuC842/ADuC843 are complete smart 32 kHz external crystal, on-chip programmable PLL transducer front ends, that integrates a high performance self- 12 interrupt sources, 2 priority levels calibrating multichannel ADC, a dual DAC, and an optimized Dual data pointers, extended 11-bit stack pointer single-cycle 20 MHz 8-bit MCU (8051 instruction set compatible) On-chip peripherals on a single chip. Time interval counter (TIC) 2 The ADuC841 and ADuC842 are identical with the exception UART, I C, and SPI Serial I/O of the clock oscillator circuit the ADuC841 is clocked directly Watchdog timer (WDT) from an external crystal up to 20 MHz whereas the ADuC842 Power supply monitor (PSM) uses a 32 kHz crystal with an on-chip PLL generating a Power programmable core clock up to 16.78 MHz. Normal: 4.5 mA 3 V (core CLK = 2.098 MHz) 2 Power-down: 10 A 3 V The ADuC843 is identical to the ADuC842 except that the Development tools ADuC843 has no analog DAC outputs. Low cost, comprehensive development system The microcontroller is an optimized 8052 core offering up to incorporating nonintrusive single-pin emulation, 20 MIPS peak performance. Three different memory options IDE based assembly and C source debugging are available offering up to 62 kBytes of nonvolatile Flash/EE APPLICATIONS program memory. Four kBytes of nonvolatile Flash/EE data Optical networkinglaser power control memory, 256 bytes RAM, and 2 kBytes of extended RAM are Base station systems also integrated on-chip. Precision instrumentation, smart sensors Transient capture systems 1 Protected by U.S. Patent No. 5,969,657. DAS and communications systems (continued on page 23) 1 ADuC841/ADuC842 only. 2 ADuC842/ADuC843 only, ADuC841 driven directly by external crystal. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20032017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com 03260-0-001ADuC841/ADuC842/ADuC843 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 User Interface to On-Chip Peripherals.................................... 46 Applications ....................................................................................... 1 On-Chip PLL .............................................................................. 49 Functional Block Diagram .............................................................. 1 Pulse-Width Modulator (PWM) .............................................. 50 General Description ......................................................................... 1 Serial Peripheral Interface (SPI) ............................................... 53 2 Revision History ............................................................................... 2 I C Compatible Interface ........................................................... 56 Specifications ..................................................................................... 3 Dual Data Pointer ....................................................................... 59 Absolute Maximum Ratings ............................................................ 8 Power Supply Monitor ............................................................... 60 ESD Caution .................................................................................. 8 Watchdog Timer ......................................................................... 61 Pin Configurations and Function Descriptions ........................... 9 Time Interval Counter (TIC) .................................................... 62 Terminology .................................................................................... 19 8052 Compatible On-Chip Peripherals ................................... 65 ADC Specifications .................................................................... 19 Timer/Counter 0 and 1 Operating Modes .............................. 70 DAC Specifications..................................................................... 19 Timer/Counter Operating Modes ............................................ 72 Typical Performance Characteristics ........................................... 20 UART Serial Interface ................................................................ 73 Functional Description .................................................................. 24 SBUF ............................................................................................ 73 8052 Instruction Set ................................................................... 24 Interrupt System ......................................................................... 78 Other Single-Cycle Core Features ............................................ 26 Hardware Design Considerations ............................................ 80 Memory Organization ............................................................... 27 Other Hardware Considerations .............................................. 84 Special Function Registers (SFRs) ............................................ 28 Development Tools .................................................................... 85 Accumulator SFR (ACC) ........................................................... 29 QuickStart Development System ............................................. 85 , , Special Function Register Banks .............................................. 30 Timing Specifications .................................................................. 86 ADC Circuit Information.......................................................... 31 Outline Dimensions ....................................................................... 94 Calibrating the ADC .................................................................. 38 Ordering Guide .......................................................................... 95 Nonvolatile Flash/EE Memory ................................................. 39 Using Flash/EE Data Memory .................................................. 42 REVISION HISTORY Changes to Figure 4 ........................................................................ 14 6/2017Rev. A to Rev. B Added Table 4 Renumbered Sequentially .................................. 14 Change to Notes, Figure 4 ............................................................. 14 Changes to Using the DAC Section ............................................. 47 Changes to Figure 96 ...................................................................... 95 Updated Outline Dimensions ....................................................... 94 Changes to Ordering Guide .......................................................... 95 4/2016Rev. 0 to Rev. A Added Patent Note, Note 1 .............................................................. 1 11/2003Revision 0: Initial Version Changes to Figure 3 and Table 3 ..................................................... 9 Rev. B Page 2 of 95