Low Power, Chip Scale, 10-Bit SD/HD Video Encoder Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 FEATURES Gamma correction Programmable adaptive filter control 3 high quality, 10-bit video DACs Programmable sharpness filter control 16 (216 MHz) DAC oversampling for SD CGMS (720p/1080i) and CGMS Type B (720p/1080i) 8 (216 MHz) DAC oversampling for ED Dual data rate (DDR) input support 4 (297 MHz) DAC oversampling for HD Enhanced definition (ED) programmable features 37 mA maximum DAC output current (525p/625p) Multiformat video input support 8 oversampling (216 MHz output) 4:2:2 YCrCb (SD, ED, and HD) Internal test pattern generator 4:4:4 RGB (SD) Black bar, hatch, flat field/frame Multiformat video output support Individual Y and PrPb output delay Composite (CVBS) and S-Video (Y-C) Gamma correction Component YPrPb (SD, ED, and HD) Programmable adaptive filter control Component RGB (SD, ED, and HD) Fully programmable YCrCb to RGB matrix Lead frame chip scale package (LFCSP) options Undershoot limiter 32-lead, 5 mm 5 mm LFCSP Macrovision Rev 1.2 (525p/625p) (ADV7390/ADV7392 only) 40-lead, 6 mm 6 mm LFCSP CGMS (525p/625p) and CGMS Type B (525p) Wafer level chip scale package (WLCSP) option Dual data rate (DDR) input support 30-ball, 5 6 WLCSP with single DAC output Standard definition (SD) programmable features Advanced power management 16 oversampling (216 MHz) Patented content-dependent low power DAC operation Internal test pattern generator Automatic cable detection and DAC power-down Color and black bar Individual DAC on/off control Controlled edge rates for start and end of active video Sleep mode with minimal power consumption Individual Y and PrPb output delay 74.25 MHz 8-/10-/16-bit high definition input support Undershoot limiter Compliant with SMPTE 274M (1080i), 296M (720p), Gamma correction and 240M (1035i) Digital noise reduction (DNR) EIA/CEA-861B compliance support Multiple chroma and luma filters NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support Luma-SSAF filter with programmable gain/attenuation NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz) PrPb SSAF Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant Separate pedestal control on component and Copy generation management system (CGMS) composite/S-Video output Closed captioning and wide screen signaling (WSS) VCR FF/RW sync mode Integrated subcarrier locking to external video source Macrovision Rev 7.1.L1 (ADV7390/ADV7392 only) Complete on-chip video timing generator Copy generation management system (CGMS) On-chip test pattern generation Wide screen signaling (WSS) Programmable features Closed captioning Luma and chroma filter responses 2 Serial MPU interface with I C compatibility Vertical blanking interval (VBI) 2.7 V or 3.3 V analog operation Subcarrier frequency (f ) and phase SC 1.8 V digital operation Luma delay 1.8 V or 3.3 V I/O operation High definition (HD) programmable features Temperature range: 40C to +85C (720p/1080i/1035i) W Grade automotive range: 40C to +105C 4 oversampling (297 MHz) Qualified for automotive applications Internal test pattern generator Color and black bar, hatch, flat field/frame Fully programmable YCrCb to RGB matrix Rev. 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Technical Support www.analog.com ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet TABLE OF CONTENTS ED/HD Timing Reset ................................................................ 51 Features .............................................................................................. 1 SD Subcarrier Frequency Lock ................................................. 51 Revision History ............................................................................... 3 SD VCR FF/RW Sync ................................................................ 52 Applications ....................................................................................... 5 Vertical Blanking Interval ......................................................... 52 General Description ......................................................................... 5 SD Subcarrier Frequency Control ............................................ 52 Functional Block Diagrams ............................................................. 6 SD Noninterlaced Mode ............................................................ 52 Specifications ..................................................................................... 7 SD Square Pixel Mode ............................................................... 53 Power Supply Specifications........................................................ 7 Filters ............................................................................................ 54 Input Clock Specifications .......................................................... 7 ED/HD Test Pattern Color Controls ....................................... 55 Analog Output Specifications ..................................................... 7 Color Space Conversion Matrix ............................................... 55 Digital Input/Output Specifications3.3 V ............................. 8 SD Luma and Color Scale Control ........................................... 57 Digital Input/Output Specifications1.8 V ............................. 8 SD Hue Adjust Control .............................................................. 57 MPU Port Timing Specifications ............................................... 8 SD Brightness Detect ................................................................. 57 Digital Timing Specifications3.3 V ........................................ 9 SD Brightness Control ............................................................... 57 Digital Timing Specifications1.8 V ...................................... 10 SD Input Standard Autodetection ............................................ 58 Video Performance Specifications ........................................... 11 Double Buffering ........................................................................ 58 Power Specifications .................................................................. 11 Programmable DAC Gain Control .......................................... 58 Timing Diagrams ........................................................................ 12 Gamma Correction .................................................................... 59 Absolute Maximum Ratings .......................................................... 18 ED/HD Sharpness Filter and Adaptive Filter Controls ......... 60 Thermal Resistance .................................................................... 18 ED/HD Sharpness Filter and Adaptive Filter Application ESD Caution ................................................................................ 18 Examples ...................................................................................... 61 Pin Configurations and Function Descriptions ......................... 19 SD Digital Noise Reduction ...................................................... 62 Typical Performance Characteristics ........................................... 21 SD Active Video Edge Control ................................................. 64 MPU Port Description ................................................................... 26 External Horizontal and Vertical Synchronization Control . 65 2 I C Operation .............................................................................. 26 Low Power Mode ........................................................................ 66 Register Map Access ....................................................................... 28 Cable Detection .......................................................................... 66 Register Programming ............................................................... 28 DAC Autopower-Down ............................................................. 66 Subaddress Register (SR7 to SR0) ............................................ 28 Sleep Mode .................................................................................. 66 ADV7390/ADV7391 Input Configuration ................................. 46 Pixel and Control Port Readback ............................................. 67 Standard Definition .................................................................... 46 Reset Mechanisms ...................................................................... 67 Enhanced Definition/High Definition .................................... 46 SD Teletext Insertion ................................................................. 67 Enhanced Definition (at 54 MHz) ........................................... 46 Printed Circuit Board Layout and Design .................................. 69 ADV7392/ADV7393 Input Configuration ................................. 47 Unused Pins ................................................................................ 69 Standard Definition .................................................................... 47 DAC Configurations .................................................................. 69 Enhanced Definition/High Definition .................................... 48 Video Output Buffer and Optional Output Filter .................. 69 Enhanced Definition (at 54 MHz) ........................................... 48 Printed Circuit Board (PCB) Layout ....................................... 70 Output Configuration .................................................................... 49 Additional Layout Considerations for the WLCSP Package 71 Design Features ............................................................................... 50 Typical Applications Circuits .................................................... 72 Output Oversampling ................................................................ 50 Copy Generation Management System ....................................... 74 HD Interlace External HSYNC and VSYNC Considerations SD CGMS .................................................................................... 74 ....................................................................................................... 51 Rev. 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