Circuit Note CN-0216 Devices Connected/Referenced Low Power, Buffered, 24-Bit Sigma-Delta AD7791 Circuits from the Lab reference circuits are engineered and ADC tested for quick and easy system integration to help solve todays Precision, Ultralow Noise, Rail-to-Rail analog, mixed-signal, and RF design challenges. For more ADA4528-1 Input/Output, Zero-Drift Op Amp information and/or support, visit www.analog.com/CN0216. High Accuracy anyCAP 100 mA Low ADP3301 Dropout Linear Regulator Precision Weigh Scale Design Using the AD7791 24-Bit Sigma-Delta ADC with External ADA4528-1 Zero-Drift Amplifiers Ultralow noise, low offset voltage, and low drift amplifiers are EVALUATION AND DESIGN SUPPORT used at the front end for amplification of the low-level signal Circuit Evaluation Boards from the load cell. The circuit yields 15.3 bit noise-free code CN-0216 Circuit Evaluation Board (EVAL-CN0216-SDPZ) resolution for a load cell with a full-scale output of 10 mV. System Demonstration Platform (EVAL-SDP-CB1Z) Design and Integration Files This circuit allows great flexibility in designing a custom low- Schematics, Layout Files, Bill of Materials level signal conditioning front end that gives the user the ability to easily optimize the overall transfer function of the combined CIRCUIT FUNCTION AND BENEFITS sensor-amplifier-converter circuit. The AD7791 maintains good The circuit in Figure 1 is a precision weigh scale signal performance over the complete output data range, from 9.5 Hz conditioning system. It uses the AD7791, a low power buffered to 120 Hz, which allows it to be used in weigh scale applications 24-bit sigma-delta ADC along with two external ADA4528-1 that operate at various low speeds. zero-drift amplifiers. This solution allows for high dc gain with a single supply. +5.0V 0.1F 10F +5.0V ADA4528-1 VDD AD7791 100pF SDP BOARD R1 11.3k REFIN(+) AND 1F SUPPORT CIRCUITS REFIN() C1 3.3F 100pF DIN RG 33 +5.0V 60.4 DOUT/RDY 33 LOAD CELL: C2 3.3F SCLK TEDEA HUNTLEIGH SENSE+ 33 1F C3 505H-0002-F070 R3 1k CS AIN(+) R2 11.3k 33 OUT OUT+ 10F C5 +5.0V AIN() R4 1k 1F C4 ADA4528-1 SENSE GND 5.0V ADP3301-5.0 V IN IN OUT IN OUT 10F 0.1F 0.1F 4.7F SD NR ERR GND Figure 1. Weigh Scale System Using the AD7791 (Simplified Schematic, All Connections and Decoupling Not Shown) Rev. 0 Circuits from the Lab circuits from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and determining its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices Tel: 781.329.4700 www.analog.com be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) Fax: 781.461.3113 2011 Analog Devices, Inc. All rights reserved. 10164-001CN-0216 Circuit Note CIRCUIT DESCRIPTION The two ADA4528-1 op amps are configured as the first stage of Figure 2 shows the actual test setup. For testing purposes, a a three op amp instrumentation amplifier. A third op amp 6-wire Tedea-Huntleigh 505H-0002-F070 load cell is used. connected as a difference amplifier would normally be used for Current flowing through a PCB trace produces an IR voltage the second stage, but in the circuit of Figure 1, the differential drop, and with longer traces, this voltage drop can be several input of the AD7791 performs this function. millivolts or more, introducing a considerable error. A 1 inch The gain is equal to 1 + 2R1/RG. Capacitors C1 and C2 are long, 0.005 inch wide trace of 1 oz copper has a resistance of placed in the feedback loops of the op amps and form 4.3 Hz approximately 100 m at room temperature. With a load cutoff frequency low-pass filters with R1 and R2. This limits the current of 10 mA, this can introduce a 1 mV error. amount of noise entering the sigma-delta ADC. C5 in conjunction with R3 and R4 form a differential filter with a A 6-wire load cell has two sense pins, in addition to the excitation, ground, and two output connections. The sense pins cutoff frequency of 8 Hz, which further limits the noise. C3 and are connected to the high side (excitation pin) and low side C4 in conjunction with R3 and R4 form common-mode filters (ground pin) of the Wheatstone bridge. The voltage developed with a cutoff frequency of 159 Hz. across the bridge can be accurately measured regardless of the The ADP3301 low noise regulator powers the AD7791, voltage drop due to wire resistance. In addition, the AD7791 ADA4528-1, and the load cell. In addition to decoupling accepts differential analog inputs and a differential reference as capacitors, a noise reduction capacitor is placed on the regulator well. These two sense pins are connected to the AD7791 output as recommended in the ADP3301 data sheet. It is reference inputs to create a ratiometric configuration that is essential that the regulator is low noise, because any noise on immune to low frequency changes in the power supply the power supply or ground plane introduces noise into the excitation voltage. The ratiometric connection eliminates the system and degrades the circuit performance. need for a precision voltage reference. Unlike a 6-wire load cell, a 4-wire load cell does not have sense pins, and the ADC differential reference pins are connected directly to the excitation voltage and ground. With this connection, there exists a voltage difference between the excitation pin and the reference pin on the ADC due to wire resistance. There will also be a voltage difference on the low side (ground) due to wire resistance. The system will not be completely ratiometric. The Tedea-Huntleigh 2 kg load cell has a sensitivity of 2 mV/V and a full-scale output of 10 mV when the excitation voltage is 5 V. A load cell also has an offset, or TARE, associated with it. In addition, the load cell also has a gain error. Some customers use a DAC to remove or null the TARE. When the AD7791 uses a 5 V reference, its differential analog input range is equal to 5 V, or 10 V p-p. The circuit in Figure 1 amplifies the load cell Figure 2. Weigh Scale System Setup Using the AD7791 output by a factor of 375 (1 + 2R1/RG), so the full-scale input The 24-bit sigma-delta ADC AD7791 converts the amplified range referred to the load cell output is 10 V/375 = 27 mV p-p. signal from the load cell. The AD7791 is configured to operate This extra range relative to the 10 mV p-p load cell full-scale in the buffered mode to accommodate the impedance of the signal is beneficial as it ensures that the offset and gain error of R-C filter network on the analog input pins. the load cell do not overload the ADCs front end. Figure 3 shows the AD7791s rms noise for different output data The low-level amplitude signal from the load cell is amplified by rates. This plot shows that the rms noise increases as the output two ADA4528-1 zero-drift amplifiers. A zero-drift amplifier, as data rate increases. However, the device maintains good noise the name suggests, has a close to zero offset voltage drift. The performance over the complete range of output data rates. amplifier continuously self-corrects for any dc errors, making it as accurate as possible. Besides having low offset voltage and drift, a zero-drift amplfier also exhibits no 1/f noise. This important feature allows precision weigh scale measurement at dc or low frequency. Rev. 0 Page 2 of 5 10164-002