Circuit Note CN-0269 Devices Connected/Referenced AD7984 18-Bit, 1.33 MSPS PulSAR 10.5 mW ADC in MSOP/QFN AD8475 Precision, Selectable Gain, Fully Differential Funnel Amp Circuits from the Lab reference circuits are engineered and tested for quick and easy system AD8065 High Performance, 145 MHz FastFET Op Amps integration to help solve todays analog, mixed-signal, ADG5208 High Voltage, Latch-Up Proof, 8-Channel Multiplexers and RF design challenges. For more information and/or support, visit www.analog.com/CN0269. ADG5236 High Voltage Latch-Up Proof, Dual SPDT Switches Ultralow Noise, 4.096 V, LDO XFET Voltage References with ADR444 Current Sink and Source 18-Bit, 1.33 MSPS, 16-Channel Data Acquisition System A single channel can be sampled at up to 1.33 MSPS with 18-bit EVALUATION AND DESIGN SUPPORT resolution. A channel-to-channel switching rate of 250 kHz Circuit Evaluation Boards between all input channels provides 16-bit performance. CN-0269 Circuit Evaluation Board (EVAL-CN0269-SDPZ) System Demonstration Platform (EVAL-SDP-CB1Z) The signal processing circuit combined with a simple 4-bit up- Design and Integration Files down binary counter provides a simple and cost effective way to Schematics, Layout Files, Bill of Materials realize channel-to-channel switching without an FPGA, CPLD, or high speed processor. The counter can be programmed to CIRCUIT FUNCTION AND BENEFITS count up or count down for sequentially sampling multiple The circuit shown in Figure 1 is a high performance industrial channels, or can be loaded with a fixed binary word for signal level multichannel data acquisition circuit that has been sampling a single channel. optimized for fast channel-to-channel switching. It can process 16-channels of single-ended inputs or 8-channels of differential inputs with up to 18-bit resolution. +5V +12V SINGLE ENDED +2.5V TP 1 TP 2 +4.096V VDD VIN NC 2 P4 0.1F NC 1 VOUT S1 D 0.1F 22F 0.1F AI0 AI0+ 50V GND TRIM S2 50V 6.3V 50V AI1 AI1+ AGND DGND S3 AI2 AI2+ ADR444 S4 AI3 AI3+ S5 AI4 AI4+ S6 AI5 AI5+ +5V +12V 12V AD8065 S7 AI6 AI6+ S8 1k 0 AI7 AI7+ VCOM VIO VDD VSS JP3 +VS +12V 12V NC 1.25k 1k 10k EN GND SPORT 1 10 A0 S1A 2 IN 0.4* 1k 1.25k VSS A1 D1 2.2nF VDD VIO REF +OUT A2 IN+ SDI GND S1B 3 IN 0.8* 0.1F 12V 33 IN1 VCOM SCK TCLKBF 33 ADG5208 2.2nF SDO S2A DATA +12V 33 1.25k OUT 1k +IN 0.8* D2 3 IN CNV TFS GND S2B 10 2 +IN 0.4* IN2 AD7984 1 1.25k +12V NC 1 JP4 VS 12V NC 2 NC 4 NC 3 NC 5 AD8475 +3.3V 1k VDD AD8065 GPIO ADG5236 S1 D 15 VCC AI8 AI0 S2 CP AI9 AI1 GND S3 AI10 AI2 CEP S4 AI11 AI3 CET PE PL S5 AI12 AI4 CH0 CH1 CH2 CH3 TC U/D U/D S6 AI13 AI5 33 S7 AI14 AI6 Q0 P0 P0 S8 33 AI15 AI7 Q1 P1 P1 33 Q2 P2 P2 12V EN Q3 P3 B P3 33 A0 Y 74LVC1G00 DIFFERENTIAL 74LVC169 A1 A VSS 33 A2 GND S D 33 EN ADG5208 Figure 1. Multichannel Data Acquisition Circuit (Simplified Schematic: All Components, Connections, and Decoupling Not Shown) Rev. 0 Circuits from the Lab circuits from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and determining its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices Tel: 781.329.4700 www.analog.com be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) Fax: 781.461.3113 2013 Analog Devices, Inc. All rights reserved. 10563-001CN-0269 Circuit Note signals by modern low voltage differential input ADCs, the This circuit is an ideal solution for a multichannel data attenuation and level shifting stage is necessary. acquisition card for many industrial applications including process control, and power line monitoring. The AD8475, fully differential, attenuating (funnel) amplifier with integrated precision gain resistors provides precision attenuation CIRCUIT DESCRIPTION (by 0.4 or 0.8), common-mode level shifting, and single- The circuit shown in Figure 1 is a classic multichannel non- ended-to-differential conversion along with input overvoltage synchronous data acquisition signal chain consisting of a protection. Fast settling time (50 ns to 0.001%), and low noise multiplexer, amplifiers, and an ADC. performance (10 nV/Hz) make the AD8475 well suited to drive 18-bit differential input ADCs at sampling rates up to 4 MSPS. The architecture allows fast sampling of multiple channels using a single ADC, providing low cost and excellent channel-to- The AD7984, 18-bit, PulSAR ADC selected in this circuit channel matching. provides 18-bit resolution at 1.33 MSPS when sampling a single Channel-to-channel switching speed is limited by the settling channel. However, the settling time of various components in time of the various components following the multiplexer in the the signal chain limit the overall accuracy when sequentially signal chain, because the multiplexer can present a full-scale switching between channels. For example, 16-bit performance is step voltage output to the downstream amplifier and ADC. The achieved when switching between channels at a 250 kHz rate. components in this circuit have been specifically chosen to Timing Analysis minimize the settling time and maximize channel-to-channel When the circuit shown in Figure 1 is operating in the continuous switching speed. switching mode, all the 16-channel signal-ended or 8-channel Component Selection differential signal streams are merged into a time-division The ADG5208 multiplexer switches one of eight inputs to a multiplexed signal by the two stage multiplexer comprised of common output, as determined by the 3-bit binary address the ADG5208 and the ADG5236. The multiplexed signal drives the buffer circuit (AD8065) and the attenuation and level shift lines. The ADG5236 contains two independently selectable circuit (AD8475). The output signal of the AD8475 drives the single-pole/double throw (SPDT) switches. Two ADG5208 differential input ADC through an RC filter (2.2 nF, 10 ). switches, combined with one ADG5236, allow 16 single-ended channels or 8 true differential channels to be connected to the The multiplexed input signal typically consists of large voltage rest of the signal chain using a 4-bit digital control signal. steps when switching between channels. In the worst case, one The 4-bit digital signal is generated by a 4-bit binary up/down channel is at negative full scale, while the next channel is at counter triggered by the same signal used for the convert (CNV) positive full scale. Therefore, the step can be as large as the full input to the 18-bit, 1.33 MSPS AD7984 ADC. range of input signal, in this case, 20 V. It is a tremendous challenge for the analog signal chain to settle to high precision from such The AD8065 JFET input op amp has a 145 MHz bandwidth and a large step signal level in a short time. The timing of the circuit is configured as a unity-gain buffer to provide excellent settling must be carefully examined to determine the amount of settling time performance and extremely high input impedance. The time available at various sampling rates and the settling time AD8065 also provides very low impedance output to drive the required by the circuits in the signal chain. AD8475 funnel amp attenuation stage. Figure 2 shows the basic timing diagram of the system, and this The advantages of fully differential signal chain are good is where the analysis starts. common-mode rejection and reduction in second-order distortion products. In order to process 10 V industrial level t S CNV t t CONV ACQ STATUS ACQUISITION CONVERSION ACQUISITION 0000 0001 CH3 TO CH0 SETTLING TO CH0 SETTLING TO CH1 V SW OUT t t t DD MD SETTLE Figure 2. Multichannel Data Acquisition Circuit Timing Rev. 0 Page 2 of 12 10563-002