Circuit Note CN-0335 Devices Connected/Referenced Precision, Low Noise, Dual CMOS, Rail- AD8606 Circuits from the Lab reference designs are engineered and to-Rail Input/Output Op Amp tested for quick and easy system integration to help solve todays analog, mixed-signal, and RF design challenges. For more AD7091R 1 MSPS, Ultralow Power, 12-Bit ADC information and/or support, visit CN-0335 Circuit Note Galvanic isolation is provided by the ADuM5401 (C-Grade) CIRCUIT DESCRIPTION quad channel digital isolator. In addition to the isolated output The circuit consists of an input signal conditioning stage, an data, the ADuM5401 also provides isolated 3.3 V for the circuit. ADC stage, and an output isolation stage. The 10 V input The ADuM5401 is not required for normal circuit operation signal is level shifted and attenuated by the U1A op amp that is unless isolation is needed. The ADuM5401 quad-channel, one-half of the dual AD8606. The output of the op amp is 0.1 V 2.5 kV isolators with integrated dc-to-dc converter, is available to 2.4 V, which matches the input range of the ADC (0 V to in a small 16-lead SOIC. Power dissipation of the ADuM5401 2.5 V) with 100 mV headroom to maintain linearity. The with a 7 MHz clock is approximately 140 mW. buffered voltage reference (VREF =2.5 V) from the ADC is used The AD7091R requires a 50 MHz serial clock (SCLK) to achieve to generate the required offset. Resistor values can be modified a 1 MSPS sampling rate. However, the ADuM5401 (C-grade) to accommodate other popular input ranges as described later isolator has a maximum data rate of 25 Mbps that corresponds in this circuit note. to a maximum serial clock frequency of 12.5 MHz. In addition, The circuit design allows single supply operation. The minimum the SPI port requires that the trailing edge of the SCLK clock output voltage specification of the AD8606 is 50 mV for a 2.7 V the output data into the processor, therefore the total round-trip power supply and 290 mV for 5 V power supply with 10 mA propagation delay through the ADuM5401 (120 ns maximum) load current, over the temperature range of 40C to +125C. A limits the upper clock frequency to 1/120 ns = 8.3 MHz. minimum output voltage of 45 mV to 60 mV is a conservative Even though the AD7091R is a 12-bit ADC, the serial data is estimate for a 3.3 V power supply, a load current less than formatted into a 16-bit word to be compatible with the processor 1 mA, and a narrower temperature range. serial port requirements. The sampling period, TS, therefore Considering the tolerances of the parts, the minimum output consists of the AD7091R 650 ns conversion time plus 58 ns voltage (low limit of the range) is set to 100 mV to allow a safety (extra time required from data sheet, t1 delay + tQUIET delay) plus margin. The upper limit of the output range is set to 2.4 V in 16 clock cycles for the SPI interface data transfer. order to give 100 mV headroom for the positive swing at the T = 650 ns + 58 ns + 16 120 ns = 2628 ns S ADC input. Therefore, the nominal output voltage range of the input op amp is 0.1 V to 2.4 V. f = 1/T = 1/2628 ns = 380 kSPS S S The second half of the AD8606 (U1B) is used to buffer the In order to provide a safety margin, a maximum SCLK of internal 2.5 V voltage reference of the AD7091R (U3) ADC. 7 MHz and a maximum sampling rate of 300 kSPS is recommended. The digital SPI interface can be connected to the The AD8606 is chosen for this application because of its low offset microprocessor evaluation board using the 12-pin Pmod- voltage (65 V maximum), low bias current (1 pA maximum) compatible connector (Digilent Pmod Specifications). and low noise (12 nV/Hz maximum). Power dissipation is only 9.2 mW on a 3.3 V supply. Circuit Design The circuit shown in Figure 2 attenuates and level shifts the 10 V A single-pole RC filter (R3/C9) follows the op amp output stage to reduce the out-of-band noise. The cutoff frequency of the RC to +10 V input signal to the ADC input range of 0.1 V to 2.4 V. filter is set to 664 kHz. An optional second order filter (R4, C10, R1 R2 52. 3k 12k and R1, R2, C11) can be added to reduce the filter cutoff frequency +3.3V even further in case of low frequency industrial noise. In such U1A OUTPUT GND ISO case, the sampling rate of the AD7091R can be reduced because 1/2 AD8606 +0.1V TO +2.4V of the lower signal bandwidth. The AD7091R 12-bit 1 MSPS SAR ADC is chosen because of its GND ISO INPUT ultralow power 349 A at 3.3 V (1.2 mW) which is significantly R4 R5 10V TO +10V GND ISO 52. 3k 12k VREF 1 lower than any competitive ADC currently available in the market. 2.5V R6 2 The AD7091R also contains an internal 2.5 V reference with 10k o 4.5 ppm/ C typical drift. The input bandwidth is 7.5 MHz, GND ISO GND ISO and the high speed serial interface is SPI compatible. The Figure 2. Input Voltage Signal Conditioning Circuit AD7091R is available in a small footprint 10-lead MSOP. The total power dissipation of the circuit (excluding the ADuM5401 isolator) is approximately 10.4 mW when operating on a 3.3 V supply. Rev. A Page 2 of 8 11649-002