Circuit Note CN-0336 Devices Connected/Referenced Precision, Low Noise, CMOS, Rail-to-Rail Circuits from the Lab reference designs are engineered and AD8606 Input/Output Op Amp tested for quick and easy system integration to help solve todays analog, mixed-signal, and RF design challenges. For more AD7091R 1 MSPS, Ultralow Power, 12-Bit ADC information and/or support, visit www.analog.com/CN0336. 4-Channel, 2.5 kV Isolators with ADuM5401 Integrated DC-to-DC Converter 12-Bit, 300 kSPS, Single-Supply, Fully Isolated, Data Acquisition System for 4-20 mA Inputs The system processes 4 mA to 20 mA input signals using a single EVALUATION AND DESIGN SUPPORT 3.3 V supply. The total error after room temperature calibration Circuit Evaluation Boards is 0.06% FSR over a 10C temperature change, making it ideal CN0336 Circuit Evaluation Board (EVAL-CN0336-PMDZ) for a wide variety of industrial measurements SDP/PMD Interposer Board (SDP-PMD-IB1Z) The small footprint of the circuit makes this combination an System Demonstration Platform (EVAL-SDP-CB1Z) industry-leading solution for 4 mA to 20 mA data acquisition Design and Integration Files systems where the accuracy, speed, cost, and size play a critical Schematics, Layout Files, Bill of Materials role. Both data and power are isolated, thereby making the CIRCUIT FUNCTION AND BENEFITS circuit robust to high voltages and also ground-loop interference The circuit shown in Figure 1 is a completely isolated 12-bit, often encountered in harsh industrial environments. 300 kSPS data acquisition system utilizing only three active devices. U1B 1/2 AD8606 VREF U2 2.5V ADuM5401 (C-GRADE) +3.3V +3.3V +3.3V V V +3.3V IN ISO DD1 R4 GND GND1 GND ISO J2 5.11k D1 TP1 REF V V V SS CS OUT DD OA IA I 1N4148 0.1V TO 2.4V U1A IN R1 SCLK V V SCK 1/2 AD8606 OB IB U3 V V CONVST V CONVST INPUT OC IC IN AD7091R C10 R2 4mA TO 20mA C11 V V MISO SDO 51 ID OD 4.7nF V +3.3V GND REGCAP V RC R3 DRIVE SEL OUT GND ISO GND ISO 120 GND GND1 GND ISO GND ISO C8 R5 1F PMOD CON 1k GND ISO R6 12-PIN 124k J1 GND ISO GND ISO GND ISO Figure 1. 4 mA to 20 mA Single Supply Analog to Digital Conversion with Isolation (All Connections and Decoupling Not Shown) Rev. A Circuits from the Lab reference designs from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. determining its suitability and applicability for your use and application. Accordingly, in no event shall Tel: 781.329.4700 www.analog.com Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) Fax: 781.461.3113 2014 Analog Devices, Inc. All rights reserved. 11650-001CN-0336 Circuit Note The total power dissipation of the circuit (excluding the CIRCUIT DESCRIPTION ADuM5401 isolator) is approximately 10.4 mW when The circuit consists of an input current-to-voltage converter, a operating on a 3.3 V supply. level shifting circuit, an ADC stage, and an output isolation stage. The 4 mA to 20 mA input signal is converted to a voltage Galvanic isolation is provided by the ADuM5401 (C-Grade) by resistor R3. For R3 = 120 and an input current of 4 mA to quad channel digital isolator. In addition to the isolated output 20 mA, the input voltage to the level shifting circuit is: 0.48 V to data, the ADuM5401 also provides isolated +3.3 V for the 2.4 V. The diode D1 is used for protection against an accidental circuit. The ADuM5401 is not required for normal circuit operation unless isolation is needed. The ADuM5401 quad- reverse connection of the input current source. channel, 2.5 kV isolators with integrated dc-to-dc converter, is The voltage across R3 is level shifted and attenuated by the available in a small 16-lead SOIC. Power dissipation of the U1A op amp that is one-half of the dual AD8606. The output of ADuM5401 with a 7 MHz clock is approximately 140 mW. the op amp is 0.1 V to 2.4 V which matches the input range of the ADC (0 V to 2.5 V) with 100 mV headroom to maintain The AD7091R requires a 50 MHz serial clock (SCLK) to achieve linearity. The buffered voltage reference (V = 2.5 V) from the a 1 MSPS sampling rate. However, the ADuM5401 (C-grade) REF AD7091R ADC is used to generate the required offset. Resistor isolator has a maximum data rate of 25 Mbps that corresponds to a maximum serial clock frequency of 12.5 MHz. In addition, values can be modified to accommodate other popular input the SPI port requires that the trailing edge of the SCLK clock ranges as described later in this circuit note. the output data into the processor, therefore the total round-trip The circuit design allows single-supply operation. The propagation delay through the ADuM5401 (120 ns maximum) minimum output voltage specification of the AD8606 is 50 mV limits the upper clock frequency to 1/120 ns = 8.3 MHz. for a 2.7 V power supply and 290 mV for 5 V power supply with 10 mA load current, over the temperature range of -40C to Even though the AD7091R is a 12-bit ADC, the serial data is +125C. A minimum output voltage of 45 mV to 60 mV is a formatted into a 16-bit word to be compatible with the processor conservative estimate for a 3.3 V power supply, a load current serial port requirements. The sampling period, TS, therefore consists of the AD7091R 650 ns conversion time plus 58 ns less than 1 mA, and a narrower temperature range. (extra time required from data sheet, t delay + t delay) plus 1 QUIET Considering the tolerances of the parts, the minimum output 16 clock cycles for the SPI interface data transfer. voltage (low limit of the range) is set to 100 mV to allow for a safety margin. The upper limit of the output range is set to 2.4 V TS = 650 ns + 58 ns + 16 120 ns = 2628 ns in order to give 100 mV headroom for the positive swing at the fS = 1/TS = 1/2628 ns = 380 kSPS ADC input. Therefore, the nominal output voltage range of the In order to provide a safety margin, a maximum SCLK of 7 MHz input op amp is 0.1 V to 2.4 V. and a maximum sampling rate of 300 kSPS is recommended. The second half of the AD8606 (U1B) is used to buffer the The digital SPI interface can be connected to the microprocessor internal 2.5 V voltage reference of the AD7091R (U3) ADC. evaluation board using the 12-pin, Pmod-compatible connector (Digilent Pmod Specifications). The AD8606 is chosen for this application because of its low offset voltage (65 V maximum), low bias current (1 pA Circuit Design maximum) and low noise (12 nV/Hz maximum). Power The circuit shown in Figure 2 provides the proper gain and level dissipation is only 9.2 mW on a 3.3 V supply. shifting to shift the 0.48 V to 2.4 V signal to the ADC input A single-pole RC filter (R2/C11) follows the op amp output range of 0.1 V to 2.4 V. stage to reduce the out-of-band noise. The cutoff frequency of +3.3V the RC filter is set to 664 kHz. An optional filter (R1/C10) can I IN U1A be added to reduce the filter cutoff frequency even further in 1/2 AD8606 VREF case of low frequency industrial noise. In such case, the INPUT 2.5V OUTPUT 4mA TO 20mA R3 0.1V TO 2.4V sampling rate of the AD7091R can be reduced because of the 120 0.1% R4 GND lower signal bandwidth. 5.11k 1% The AD7091R 12-bit 1 MSPS SAR ADC is chosen because of its R5 R6 1k 124k ultralow power 349 A at 3.3 V (1.2 mW) which is significantly 1% 1% GND ISO lower than any competitive ADC currently available in the market. Figure 2. Current-to-Voltage Converter and Level Shifting Circuit The AD7091R also contains an internal 2.5 V reference with o 4.5 ppm/ C typical drift. The input bandwidth is 7.5 MHz, and the high speed serial interface is SPI compatible. The AD7091R is available in a small footprint 10-lead MSOP. Rev. A Page 2 of 7 11650-002