Circuit Note CN-0337 Devices Connected/Referenced Precision, Low Noise, CMOS, Rail to Rail AD8608 Circuits from the Lab reference designs are engineered and Input/Output Quad Op Amp tested for quick and easy system integration to help solve todays analog, mixed-signal, and RF design challenges. For more AD7091R 1 MSPS, Ultralow Power, 12-Bit ADC information and/or support, visit www.analog.com/CN0337. 4-Channel, 2.5 kV Isolators with ADuM5401 Integrated DC-to-DC Converter 12-Bit, 300 kSPS, Single-Supply, Fully Isolated RTD Temperature Measurement System with 3-Wire Compensation The small footprint of the circuit makes this combination an EVALUATION AND DESIGN SUPPORT industry-leading solution for temperature measurements where Circuit Evaluation Boards accuracy, cost, and size play a critical role. Both data and power CN0337 Circuit Evaluation Board (EVAL-CN0337-PMDZ) are isolated, thereby making the circuit robust to high voltages SDP/PMD Interposer Board (SDP-PMD-IB1Z) and also ground-loop interference often encountered in harsh System Demonstration Platform (EVAL-SDP-CB1Z) industrial environments. Design and Integration Files Schematics, Layout Files, Bill of Materials The novel circuit for 3-wire RTD lead wire compensation was developed by Hristo Ivanov Gigov, Associate Professor and PhD, CIRCUIT FUNCTION AND BENEFITS and Stanimir Krasimirov Stankov, Engineer and PhD Student, The circuit shown in Figure 1 is a completely isolated 12-bit, Department of Electronic Engineering and Microelectronics, 300 kSPS RTD temperature measuring system that uses only Technical University of Varna, Varna, Bulgaria. three active devices. The system processes the output of a Pt100 RTD and includes an innovative circuit for lead-wire compensation using a standard 3-wire connection. The circuit operates on a single 3.3 V supply. The total error after room temperature calibration is less than 0.24% FSR for a 10C change in temperature, making it ideal for a wide variety of industrial temperature measurements. U1B R5 1/4 VREF A J1 AD8608 ADuM5401 +3.3V +3.3V PMOD CON 2k (C-GRADE) 12-PIN J2 V R R8 U3 V V +3.3V IN ISO DD1 RTD LINE INPUT VREF +3.3V AD7091R U1C 26.7k GND GND GND ISO 1 (Pt100) R10 TP1 1/4 0.1V TO 2.4V CS V V SS r OA IA 1 1 1 AD8608 1k SCLK U1A V V SCK OB IB R11 C10 1/4 CONVST VIN V V CONVST 0.1F OC IC AD8608 51 R = R + R C9 X 0 SDO V V MISO 2 ID OD 4.7nF V V RC R1 R6 DRIVE SEL OUT r 2 2 GND GND GND R1 R2 R9 R6 R12 GND ISO ISO 1 GND ISO C12 100 1.91k 1.1k 2k 39.2k +3.3V r 3 3 3 ISOLATION B C11 1F U1D 1/4 0.1F AD8608 0C TO 300C GND ISO GND ISO GND ISO 100 TO 212.05 R3 R4 1k 39.2k R1 = R1R2 R6 = R6R12 Figure 1. Resistance Deviation to Digital Conversion with Isolation Using Pt100 RTD Sensor (All Connections and Decoupling Not Shown) Rev. 0 Circuits from the Lab reference designs from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. determining its suitability and applicability for your use and application. Accordingly, in no event shall Tel: 781.329.4700 www.analog.com Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) Fax: 781.461.3113 2014 Analog Devices, Inc. All rights reserved. REF GND OUT V REGCAP DD 11653-001CN-0337 Circuit Note A single-pole RC filter (R11/C9) follows the op amp output CIRCUIT DESCRIPTION stage to reduce the out-of-band noise. The cutoff frequency of The input stage of the circuit is an RTD signal conditioning circuit the RC filter is set to 664 kHz. Additional second order filters using a compensated 3-wire connection to the RTD. The circuit (adding capacitors C10 and C11) are used for reducing the filter translates the RTD input resistance range (100 to 212.05 cutoff frequency in case of low frequency industrial noise. In for a 0C to 300C temperature range) into voltage levels this case, AD7091R is not operating at maximum throughput compatible with the input range of the ADC (0 V to 2.5 V). rate. To increase the conversion speed C10 and C11 should be left unpopulated. The excitation current for the RTD is supplied by op amp U1C that is one-fourth of the quad AD8608. A reference voltage, VR, The AD7091R 12-bit 1 MSPS SAR ADC is chosen because of its of 100 mV is developed by the R8/R9 divider driven by the 2.5 V ultralow power 349 A at 3.3 V (1.2 mW) which is significantly ADC reference. This in turn produces an RTD excitation lower than any competitive ADC currently available in the market. current of VR/(R1 R2), approximately 1.05 mA. The AD7091R also contains an internal 2.5 V reference with o The excitation current produces a voltage change of 4.5 ppm/ C typical drift. The input bandwidth is 7.5 MHz, approximately 117.6 mV (105 mV to 222.6 mV) across the RTD and the high speed serial interface is SPI compatible. The for a temperature change of 0C to 300C. The U1A op amp AD7091R is available in a small footprint 10-lead MSOP. amplifies this voltage change by 19.6, producing an output span The total power dissipation of the circuit (excluding the of 2.3 V. Resistor R2 added in parallel with Resistor R1 shifts the ADuM5401 isolator) is approximately 20 mW when operating output range so that the U1A op amp output is 0.1 V to 2.4 V, on a 3.3 V supply. which matches the input range of the ADC (0 V to 2.5 V) with Galvanic isolation is provided by the ADuM5401 (C Grade) quad 100 mV headroom to maintain linearity. The resistor values can channel digital isolator. In addition to the isolated output data, be modified to accommodate other popular temperature ranges the ADuM5401 also provides isolated +3.3 V for the circuit. as described later in this circuit note. The ADuM5401 is not required for normal circuit operation The circuit design allows single supply operation. The minimum unless isolation is needed. The ADuM5401 quad-channel, output voltage specification for the AD8608 is 50 mV for a 2.7 V 2.5 kV isolators with integrated dc-to-dc converter, is available power supply and 290 mV for a 5 V power supply with 10 mA in a small 16-lead SOIC. Power dissipation of the ADuM5401 load current, over the temperature range of 40C to +125C. with a 7 MHz clock is approximately 140 mW. A minimum output voltage of 45 mV to 60 mV is a conservative The AD7091R requires a 50 MHz serial clock (SCLK) to achieve estimate for a 3.3 V power supply, a load current of less than a 1 MSPS sampling rate. However, the ADuM5401 (C-grade) 1 mA, and a narrower temperature range. isolator has a maximum data rate of 25 Mbps that corresponds Considering the tolerances of the parts, the minimum output to a maximum serial clock frequency of 12.5 MHz. In addition, voltage (low limit of the range) is set to 100 mV to allow for a the SPI port requires that the trailing edge of the SCLK clock safety margin. The upper limit of the output range is set to 2.4 V the output data into the processor, therefore the total round-trip in order to give 100 mV headroom for the positive swing at the propagation delay through the ADuM5401 (120 ns maximum) ADC input. Therefore, the nominal output voltage range of the limits the upper clock frequency to 1/120 ns = 8.3 MHz. op amp is 0.1 V to 2.4 V. Even though the AD7091R is a 12-bit ADC, the serial data is The op amp U1B is used to buffer the internal 2.5 V voltage formatted into a 16-bit word to be compatible with the reference of the AD7091R (U3) ADC. processor serial port requirements. The sampling period, TS, The quad AD8608 op amp is chosen for this application because of therefore consists of the AD7091R 650 ns conversion time plus its low offset voltage (75 V maximum), low bias current (1 pA 58 ns (extra time required from data sheet, t delay + t 1 QUIET delay) plus 16 clock cycles for the SPI interface data transfer. maximum), and low noise (12 nV/Hz maximum). Power dissipation is only 18.5 mW on a 3.3 V supply. T = 650 ns + 58 ns + 16 120 ns = 2628 ns S The U1D op amp provides the 3-wire correction signal that fS = 1/TS = 1/2628 ns = 380 kSPS compensates for the errors produced by the lead resistances r 1 In order to provide a safety margin, a maximum SCLK of and r . The gain from Point A to TP1 is +19.6, and the gain 2 7 MHz and a maximum sampling rate of 300 kSPS is from Point B to TP1 is 39.2. The voltage at Point A includes a recommended. The digital SPI interface can be connected to the positive error term that is equal to the voltage dropped across r 1 microprocessor evaluation board using the 12-pin Pmod- and r2. The voltage at Point B contains a positive error term compatible connector (Digilent Pmod Specifications). equal to the voltage dropped across r2, neglecting the small drop across r3. Because the gain from Point B to TP1 is negative and twice the gain from Point A to TP1, the errors due to the voltages dropped across r and r are cancelled, assuming that r = r . 1 2 1 2 Rev. 0 Page 2 of 8