Circuit Note CN-0350 Devices Connected/Referenced Circuits from the Lab reference designs are engineered and Precision, Low Noise, Quad CMOS, tested for quick and easy system integration to help solve todays AD8608 Rail-to-Rail Input/Output Op Amp analog, mixed-signal, and RF design challenges. For more information and/or support, visit www.analog.com/CN0350. AD7091R 1 MSPS, Ultralow Power, 12-Bit ADC 12-Bit, 1 MSPS, Single-Supply, Two-Chip Data Acquisition System for Piezoelectric Sensors CIRCUIT FUNCTION AND BENEFITS EVALUATION AND DESIGN SUPPORT Circuit Evaluation Boards The circuit shown in Figure 1 is a 12-bit, 1 MSPS data CN-0350 Circuit Evaluation Board (EVAL-CN0350-PMDZ) acquisition system utilizing only two active devices. SDP/PMD Interposer board (SDP-PMD-IB1Z) The system processes charge input signals from piezoelectric System Demonstration Platform (EVAL-SDP-CB1Z) sensors using a single 3.3 V supply and has a total error of less Design and Integration Files than 0.25% FSR after calibration over a 10C temperature Schematics, Layout Files, Bill of Materials range, making it ideal for a wide variety of laboratory and industrial measurements. The small footprint of the circuit makes this combination an industry-leading solution for data acquisition systems where accuracy, speed, cost, and size play a critical role. U1C TP6 1/4 U1B TP1 TP2 TP3 TP4 1.25V AD8608 1/4 R3 R1 AD8608 100M R10 10k 2.5V 100 C C2 CAL R2 1nF 1nF J2 10k PMOD CON +3.3V 12 PIN J1 +3.3V HREF CAL +3.3V +3.3V 4 R4 U1A U1D 1/4 VREF V 1k DD CS R5 1/4 SS POS TP5 AD8608 3 AD8608 270 R6 SCLK SCK 51 NEG U2 2 CONVST CONV VIN AD7091R C8 MISO SDATA GND 1 4.7nF GND VDRIVE HREF GND REGCAP INPUT CON R8 R7 PIEZOELECTRIC SENSOR DNP 10k +3.3V HREF C9 1F Figure 1. Charge Input Single Supply Data Acquisition System for Piezoelectric Sensors (All Connections and Decoupling Not Shown) Rev. A Circuits from the Lab reference designs from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. determining its suitability and applicability for your use and application. Accordingly, in no event shall Tel: 781.329.4700 www.analog.com Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due Fax: 781.461.3113 20142017 Analog Devices, Inc. All rights reserved. to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) 11910-001CN-0350 Circuit Note Circuit Design CIRCUIT DESCRIPTION The circuit shown in Figure 2 converts the input charge to voltage The circuit consists of an input signal conditioning stage and an and level shifts to the ADC input range of 0.1 V to 2.4 V. ADC stage. The current input signal is converted to voltage by R3 charge-to-voltage converter (charge amplifier of the U1A op amp 100M and capacitor C2) and amplified by a noninverting amplifier U1D C2 1/4 dq R5 (the U1D op amp and the R7 and R8 resistors). The buffered i = 1nF AD8608 IN 270 dt V O2 and attenuated (the U1B and U1C op amps and the resistors R1 PIEZOELECTRIC +3.3V and R2) voltage reference (VREF =2.5 V) from the ADC is used CRYSTAL R4 U1A R7 to generate an offset HREF of 1.25 V for conditioning the ac signal 1/4 POS 1k 10k AD8608 V O1 from sensor to input range of the ADC. Op amps U1A, U1B, i C IN S U1C, and U1D are one quad AD8608. The output of the U1D R8 NEG DNP S op amp is 0.1 V to 2.4 V which matches the input range of the a V = a O1 +1.25V C2 ADC (0 V to 2.5 V) with 100 mV headroom to maintain linearity. HREF a Resistor and capacitor values can be modified to accommodate (ACCELERATION) other sensor ranges as described in this circuit note. Figure 2. Charge Input Signal Conditioning Circuit The circuit design allows single supply operation. The minimum Piezoelectric elements are commonly used for the measurement output voltage specification of the AD8608 is 50 mV for a 2.7 V of acceleration and vibration. Here, the piezoelectric crystal is power supply and 290 mV for 5 V power supply with 10 mA used in conjunction with a seismic mass m. If the mass is load current, over the temperature range of 40C to +125C. subjected to an acceleration a, then there is a resulting inertial A minimum output voltage of 45 mV to 60 mV is a conservative force F = m a acting on the seismic mass and the piezoelectric estimate for a 3.3 V power supply, a load current less than 1 mA, crystal. This results in the crystal acquiring a charge q = d F, and a narrower temperature range. where d (measured in coulombs/newton, C/N) is the crystal Considering the tolerances of the parts, the minimum output charge sensitivity to force. voltage (low limit of the range) is set to 100 mV to allow for a The resulting steady-state charge sensitivity S of piezoelectric a safety margin. The upper limit of the output range is set to 2.4 V 2 accelerometer is Sa = q/a (measured in C s /m). in order to give 100 mV headroom for the positive swing at the Note that acceleration can be converted to g using the ADC input. Therefore, the nominal output voltage range of the 2 relationship 1 g = 9.81 m/s . input op amp is 0.1 V to 2.4 V. If the accelerometer is used with a charge amplifier with The AD8608 is chosen for this application because of its low feedback capacitance C2, as is shown in Figure 2, the voltage bias current (1 pA maximum), low noise (12 nV/Hz maximum) developed across C2 due to a charge q is V = q/C2. The and low offset voltage (65 V maximum). Power dissipation is corresponding steady state voltage sensitivity is: only 15.8 mW on a 3.3 V supply. S = V/a = S /C2. (1) V a A single-pole RC filter (R6/C8) follows the op amp output stage to reduce the out-of-band noise. The cutoff frequency of the RC The first stage of the signal conditioning circuit in Figure 1 is a filter is set to 664 kHz. charge amplifier (U1A and capacitor C2), where the output voltage is changing corresponding to Equation 1. The output of The AD7091R 12-bit 1 MSPS SAR ADC is chosen because of its the circuit is shifted to handle bipolar input signals (for example, ultra-low power 349 A at 3.3 V (1.2 mW) which is significantly vibration measurements). The zero of the circuit is shifted to lower than any competitive ADC currently available in the market. the middle of the input range of the ADC, using a reference of The AD7091R also contains an internal 2.5 V reference with 1.25 V. The output voltage of the charge amplifier is: 4.5 ppm/C typical drift. The input bandwidth is 7.5 MHz, and the high speed serial interface is SPI compatible. The AD7091R 1 q S a V V i dt V V a (2) O1 HREF N HREF HREF is available in a small footprint 10-lead MSOP. C2 C2 C2 The total power dissipation of the circuit is approximately The second stage of the signal conditioning circuit in Figure 1 is a 17 mW when operating on a 3.3 V supply. non-inverting amplifier with an output voltage of: The AD7091R requires a 50 MHz serial clock (SCLK) to achieve R7 S a V V 1 a (3) a 1 MSPS sampling rate. In most piezoelectric sensor applications, O2 HREF R8 C2 a lower sampling rate can be used. The test data taken in this circuit note used an SCLK of 30 MHz and a sampling rate of 300 kSPS. The digital SPI interface can be connected to the microprocessor evaluation board using the 12-pin PMOD-compatible connector (Digilent PMOD Specifications). Rev. A Page 2 of 7 11910-002