Circuit Note CN-0369 Devices Connected/Referenced ADL5801 High IP3,10 MHz to 6 GHz, Active Mixer VCO with Fo/2 & Divide-by-4 SMT, HMC512 9.6 GHz to 10.8 GHz Microwave Wideband Synthesizer with ADF4355-2 Circuits from the Lab reference designs are engineered and Integrated VCO tested for quick and easy system integration to help solve todays High Performance, 145 MHz FastFET analog, mixed-signal, and RF design challenges. For more AD8065 Op Amp information and/or support, visit www.analog.com/CN0369. Ultralow Noise, 200 mA, CMOS ADP151 Linear Regulator 800 mA Ultralow Noise, High PSRR, ADM7150 RF Linear Regulator ADF4002 Phase Detector/PLL Frequency Synthesizer Translation Phase Locked Loop Synthesizer with Low Phase Noise EVALUATION AND DESIGN SUPPORT CIRCUIT FUNCTION AND BENEFITS Circuit Evaluation Boards The circuit block diagram shown in Figure 1 is a low phase noise CN-0369 Circuit Evaluation Board (EVAL-CN0369-SDPZ) translation loop synthesizer (also known as an offset loop). This System Demonstration Platforms (EVAL-SDP-CS1Z) circuit translates the lower 100 MHz reference frequency of the ADL5801 Evaluation Board (ADL5801-EVALZ) ADF4002 phase locked loop (PLL) up to a higher frequency ADF4355-2 Evaluation Board (EV-ADF4355-2SD1Z) range of 5.0 GHz to 5.4 GHz, as determined by the frequency Design and Integration Files of the local oscillator (LO). Schematics, Layout Files, Bill of Materials The translation loop synthesizer has very low phase noise (<50 fs) in contrast to a synthesizer using only a PLL. The low phase noise is because of the very low N value used by the ADF4002 integer-N PLL, which controls the voltage controlled oscillator (VCO). In this example, the ADF4002 phase frequency detector (PFD) runs at 100 MHz, and N = 1, yielding phase noise performance that is not limited by the N value of the PLL. Rev. 0 Circuits from the Lab reference designs from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. determining its suitability and applicability for your use and application. Accordingly, in no event shall Tel: 781.329.4700 www.analog.com Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due Fax: 781.461.3113 2016 Analog Devices, Inc. All rights reserved. to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) CN-0369 Circuit Note EVAL-CN0369-SDPZ 5.5V 12V ADP151 ADM7150 ADM7150 (FINE TUNING ) 5GHz f TO REF 5.4GHz 100MHz ADF4002 ADF4355-2 HMC512 f INT N PLL OUT VCO FRAC N PLL(100MHz) RF OUT N = 1 LOW PASS FILTER AD8065 ACTIVE LOOP FILTER 100MHz f IF OUT TO ADF4002 MIXER 5GHz TO 5.4GHz ADL5801-EVALZ LOW PASS FILTER 400MHz LO 4.9GHz TO 5.3GHz 100MHz SYSTEM LOCAL OSCILLATOR CLOCK (COARSE TUNING) Figure 1. Block Diagram of the Translation Loop Synthesizer The translation loop synthesizer decouples the required channel CIRCUIT DESCRIPTION spacing from the N divider value to optimize the phase noise of In a standard PLL and VCO frequency synthesizer system, low the PLL. In this translation loop synthesizer example, N = 1. phase noise is generally the primary objective. The phase noise The translation loop synthesizer in Figure 1 locks the higher in a PLL can be described as having two components: a flat noise component known as the PLL figure of merit (FOM), and a 1/f frequency 4.8 GHz to 5.2 GHz VCO to the 100 MHz fREF signal. noise profile component known as the PLL 1/f, or flicker noise. The ADL5801 mixer and the LO together perform the divider function of this PLL. The PLL noise floor, PN , is given by TOT1 With the LO in the feedback loop, the balance equation at the PN = PN + 20log (N) + 10log (f) (1) TOT1 SYNTH 10 10 PFD ADF4002 PLL becomes where: f /R = (f f )/N REF OUT LO PNSYNTH is the synthesizer FOM and is device specific. where N and R are the N and R divider values (in this circuit, N is the divider used by the PLL. R = 1 and N = 1). fPFD is the frequency of the phase frequency detector. A PLL whose N value = 1 has a noise floor of 10log (f ). The output frequency is therefore given by 10 PFD The PLL 1/f noise, PN , is given by fOUT = fLO + fREF TOT2 PN = PN + 20log (f /1 GHz) + 10log (10 kHz/f) (2) ADF4355-2 Fractional-N Synthesizer TOT2 1/f 10 RF 10 The ADF4355-2 in this circuit provides the reference frequency where: (f ) for the translation loop as shown in Figure 2. REF PN1/f is the data sheet PLL 1/f noise at an offset of 10 kHz from the output RF frequency (normalised to a 1 GHz output). R2 fRF is the output RF frequency. C1 C3 R1 The total PLL noise, PNTOT, is given by C2 2 2 PN (PN ) (PN ) (3) TOT TOT1 TOT2 V TUNE CP OUT f This equation indicates that the noise sources add in root-sum- REF ADF4355-2 50MHz RF A OUT REF A IN WIDEBAND SYNTHESIZER 100MHz square fashion therefore, the larger noise source dominates. WITH INTEGRATED VCO A PLL with a very low N value has a phase noise dominated by Figure 2. ADF4355-2 and Loop Filter the PLL 1/f noise. Rev. 0 Page 2 of 8 12803-001 12803-002