Circuit Note CN-0388 Devices Connected/Referenced 5 kV RMS, 600 Mbps, Dual-Channel ADN4651 Circuits from the Lab reference designs are engineered and LVDS Isolator tested for quick and easy system integration to help solve todays AD7960 18-Bit, 5 MSPS PulSAR Differential ADC analog, mixed-signal, and RF design challenges. For more information and/or support, visit www.analog.com/CN0388. ADuM4400 5 kV RMS Quad-Channel Digital Isolator ADuM2251 Hot Swappable, Dual I2C Isolators, 5 kV Isolated 600 Mbps, LVDS, 18-Bit, 5 MSPS Data Acquisition System acquisition modules for industrial measurement and control. EVALUATION AND DESIGN SUPPORT Bandwidth requirements for converter interfaces are increasing, Circuit Evaluation Boards as trends such as Industry 4.0 and the Internet of Things (IoT) CN-0388 Circuit Evaluation Board (EVAL-CN0388-FMCZ) demand far more ubiquitous measurement and control, with AD7960 Evaluation Board (EVAL-AD7960-FMCZ) greater speed and precision. This poses a challenge for isolation, SDP-H1 System Demonstration Platform, High Speed because even standard digital isolators are limited to 150 Mbps (EVAL-SDP-CH1Z) operation. Design and Integration Files Schematics, Layout Files, Bill of Materials For measurement and control applications in industrial environments, the benefits of such an isolated analog front-end CIRCUIT FUNCTION AND BENEFITS implementation include: The circuit shown in Figure 1 demonstrates isolation of an analog Ease of design due to the drop-in LVDS isolator with fully front end (18-bit, 5 MSPS AD7960 analog-to-digital converter compliant input/output and ultralow jitter. (ADC)) at 600 Mbps using the ADN4651 LVDS isolator. An High bandwidth of 600 Mbps to support increased ADC interposer board with the ADN4651 connects to the standard resolution and speed. AD7960 evaluation platform, isolating the analog front end board Galvanic isolation for protection from mains voltages, from the high speed SDP-H1 system demonstration platform isolated measurement of power supplies, or noise (EVAL-SDP-CH1Z). The SDP-H1 contains a Xilinx Spartan 6 immunity from digital or power supply circuits. FPGA to capture acquisitions and a ADSP-BF527 DSP to communicate with the PC. The circuit in Figure 1 demonstrates an industry-leading solution to LVDS isolation at 600 Mbps using the ADN4651 Galvanic isolation of external interfaces is required in harsh dual-channel isolator. environments for safety, functionality, or improved noise immunity. This includes analog front ends used in data Rev. 0 Circuits from the Lab reference designs from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. determining its suitability and applicability for your use and application. Accordingly, in no event shall Tel: 781.329.4700 www.analog.com Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due Fax: 781.461.3113 2016 Analog Devices, Inc. All rights reserved. to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) CN-0388 Circuit Note ADN4651 (2) +12V DC ADA4899-1 D 100 100 D CLK 100 100 CLK XILINX SPARTAN 6 AD7960 FPGA DCO 100 100 DCO CNV 100 100 CNV EN0 TO EN3 ADA4899-1 ADuM4400 (2) EN0 TO EN3 EN0 TO EN3 1 1 2 2 PG C2M 2 PG C2M 1 LDO ENABLE USB GA0 , GA1 2 2 GA0 , GA1 1 1 (PC) ADSP-BF527 ADuM2251 GA0, GA1 SDA SDA 1 2 SDP ID SDA EEPROM SCL SCL SCL 1 2 EVAL-CN0388-FMCZ EVAL-AD7960FMCZ EVAL-SDP-CH1Z +12V DC Figure 1. EVAL-AD7960FMCZ and EVAL-SDP-CH1Z Isolated with ADN4651 EVAL-CN0388-FMCZ Interposer Board EEPROM clock (SCL) and data (SDA) from the Blackfin ADSP- CIRCUIT DESCRIPTION BF527 interface. The interposer circuit relies upon two ADN4651 600 Mbps LVDS Communications between the Blackfin ADSP-BF527 and isolators to isolate the LVDS interface to the AD7960. As shown Spartan 6 FPGA to the interposer and measurement circuits are in Figure 1, two LVDS clocks are sent from the Spartan 6 FPGA controlled through the USB port on the EVAL-SDP-CH1Z to to the AD7960 the 5 MHz sample clock (CNV) and a 300 MHz the evaluation software installed on a PC as shown in Figure 1. reference clock (CLK). The AD7960 uses the 300 MHz reference to clock out bursts of sample data at 600 Mbps on D, synchronous The circuit is powered on the logic and bus side by two 12 V dc with an echoed 300 MHz clock (DCO). D is idle after each supplies, where four supply rails are generated on the EVAL- data burst to avoid interfering with the acquisition phase of the AD7960FMCZ and three supply rails are generated on the converter. The ADN4651 houses a pair of bidirectional digital EVAL-CN0388-FMCZ. On the EVAL-AD7960FMCZ, the isolators that integrate Analog Devices, Inc., iCoupler technology ADP7104 CMOS LDO produces 5 V, the ADP7102 CMOS to operate at high speed with very low jitter. The VIN+ and VIN LDO produces 7 V, the ADP2300 nonsynchronous step-down ac voltage inputs are passed through two separate ADA4899-1 regulator produces 2.5 V, and the ADP124 CMOS linear unity-gain stable voltage feedback op amps to which their regulator produces 1.8 V. On the EVAL-CN0388-FMCZ, the corresponding outputs are fed into the AD7960. The differential ADP3335 produces 5 V, the ADP151 linear regulator (2.5 V signal of the two input signals then undergoes analog-to-digital version) produces 2.5 V, and the ADP151 linear regulator (3.3 V conversion and is sent out via D, synchronized to DCO. version) produces 3.3 V. The Blackfin ADSP-BF527 outputs the appropriate logic As shown in Figure 1, termination resistors of 100 are fitted high and logic low levels using 1.8 V logic only through the on each LVDS input and output of the two ADN4651 isolators ADuM4400 quad digital isolators to the AD7960 enable pins at CNV, CLK, D, and DCO (R11, R12, R13, and R14). (EN0 to EN3), as well as the on-board LDO enable (PC C2M) Power and ground on both the logic and bus sides are and the SDP ID EEPROM address (GA0, GA1). The enable pins connected via a barrel connector. Logic levels, clocks, and data on the AD7960 can be configured to specific operational signals are connected throughout the EVAL-AD7960FMCZ, requirements. Full information is available in the AD7960 data EVAL-CN0388-FMCZ, and EVAL-SDP-CH1Z via traces to 2 sheet. The ADuM2251 dual I C isolator isolates the SDP ID Rev. 0 Page 2 of 5 ISOLATION ISOLATION 13787-001