Circuit Note CN-0399 Devices Connected/Referenced DC to 6 GHz, 45 dB TruPwr Detector ADL5904 Circuits from the Lab reference designs are engineered and with Envelope Threshold Detection tested for quick and easy system integration to help solve todays 1 MSPS, Ultralow Power, 12-Bit ADC in analog, mixed-signal, and RF design challenges. For more AD7091R 10-Lead LFCSP and MSOP information and/or support, visit www.analog.com/CN0399. Ultralow Quiescent Current, 150 mA, ADP160 CMOS Linear Regulator Battery or USB Powered 9 kHz to 6 GHz RMS Power Measurement System This circuit constitutes a complete rms RF power meter in a EVALUATION AND DESIGN SUPPORT tiny form factor that can be powered entirely from a 5 V USB Circuit Evaluation Boards power supply. The measurement signal chain consists of an CN-0399 Circuit Evaluation Board (EVAL-CN0399-SDPZ) rms responding RF power detector and a 12-bit, precision System Demonstration Platform (EVAL-SDP-CS1Z) analog-to-digital converter (ADC). These devices are powered Design and Integration Files by a CMOS linear regulator which generates 3.3 V from the 5 V Schematics, Layout Files, Bill of Materials USB supply. CIRCUIT FUNCTION AND BENEFITS A simple calibration routine can be performed at multiple The circuit shown in Figure 1 is an RF power measurement frequencies to compensate for any frequency response variation circuit that accurately measures the power from an RF signal of the circuit. Calibration data is stored in a lookup table, which source within a frequency range of 9 kHz to 6 GHz, and has a is referenced during the RF power measurement. nominal input power range of 45 dBm (30 dBm to +15 dBm). ADL5904 SDP-S V AD7091R RFIN RMS RMS POWER INTERFACE PC 12-BIT ADC DETECTOR BOARD SPI 9kHz TO 6GHz +3.3V ADP160 +5V USB SUPPLY CMOS LINEAR EVAL-CN0399-SDPZ REGULATOR EVALUATION BOARD Figure 1. Portable RF Power Meter Evaluation Board Measurement Setup (All Connections and Decoupling Not Shown) Rev. 0 Circuits from the Lab reference designs from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. determining its suitability and applicability for your use and application. Accordingly, in no event shall Tel: 781.329.4700 www.analog.com Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) Fax: 781.461.3113 2017 Analog Devices, Inc. All rights reserved. 15768-001CN-0399 Circuit Note Analog-to-Digital Converter CIRCUIT DESCRIPTION The AD7091R shown in Figure 3 is a 12-bit, single-channel An RF signal ranging from 9 kHz to 6 GHz is applied to the successive approximation register (SAR) ADC. It has an SMA measurement head of the circuit. This signal drives the ultralow power consumption of 1 mW in normal operation. RFIN input pin of the ADL5904, an rms responding RF power REGCAP REF /REF V detector, through an ac coupling capacitor. The size of this IN OUT DD capacitor (0.47 F) sets the minimum input frequency of the circuit. The output voltage from the detector (V ) is a dc 2.5V AD7091R RMS REF output voltage level that is proportional to the rms level of the SDO input signal. SCLK SERIAL 12-BIT V T/H IN INTERFACE SAR CS The output of the detector directly drives the input of the V DRIVE AD7091R 12-bit ADC. The ADC samples the input periodically and converts the voltage to a digitized voltage code. Each code CLK OSC CONVERSION is transferred to a PC via 3-wire serial peripheral interface (SPI), CONTROL LOGIC CONVST which uses an equation to calculate the RF power of the input signal. Calibration coefficient information is stored in a look-up GND table on the PC. The coefficient slope and intercepts are selected Figure 3. AD7091R Analog-to-Digital Converter based on the frequency of operation, which must be known to The REF /REF pin of the ADC can be overdriven with an IN OUT accurately calculate the RF input power level. external reference voltage. However, in this application, accuracy RF Power Detector is not compromised by using the internal 2.5 V reference. Using The ADL5904 is a broadband rms responding RF power the 2.5 V internal reference means that the LSB size is detector operating from dc to 6 GHz. A functional block 12 LSB = (2.5 V)/2 = 610 V diagram of the ADL5904 is shown in Figure 2. This means that the ADC has a resolution of 610 V. The input ENBL VPOS VIN RST 5 7 16 15 14 voltage, V , to the ADC can range from 0 V to 2.5 V (V ). IN REF Because the maximum output voltage of the detector is ADL5904 R Q 12 Q approximately 1.8 V, voltage scaling at the input of the ADC is Q 13 Q S not necessary, allowing the detector output to be connected + directly to the ADC input. ENVELOPE 1 10 RFIN RMS VRMS On-Board Regulator DETECTOR The ADP160 is a CMOS linear regulator, which can provide a 11 3 9 4 2 6 8 stable output voltage from 2.2 V to 5.5 V with an ultralow output GND VCAL CRMS DECL DNC current quiescent current of 42 A. Figure 2. ADL5904 Block Diagram ADP160 V = 5 V = 3.3V The detector has a dynamic range of 45 dB, ranging from IN OUT 1 VIN VOUT 5 30 dBm to +15 dBm with a linear-in-dB output characteristic. 1F 1F 2 GND The low current consumption of 3 mA, makes the ADL5904 a ON suitable detector for this application circuit where the circuit is 3 EN NC 4 OFF powered entirely from the 5 V USB interface from a PC. NC = NO CONNECT An additional function provided by this detector is Figure 4. ADP160-3.3 Linear CMOS Regulator programmable envelope threshold detection. Threshold The ADP160 is available in fixed or adjustable configurations. detection uses an internal comparator to compare the input The 3.3 V fixed model used in this design provides a stable envelope voltage with a predefined user input voltage. If the output to supply the power detector and ADC, with minimal envelope voltage exceeds this predefined voltage, a digital external circuitry required, as shown in Figure 4. output signal is asserted high. The output signal is latched high through an R/S flip-flop until the reset pin (RST) on the detector is pulsed high. This functionality is not used in the circuit shown in Figure 1. Rev. 0 Page 2 of 7 15768-002 15768-004 15768-003