Circuit Note CN-0506 Devices Connected/Referenced Robust, Industrial, Low Latency and Circuits from the Lab reference designs are engineered ADIN1300 Low Power 10 Mbps, 100 Mbps, and and tested for quick and easy system integration to help solve 1 Gbps Ethernet PHY todays analog, mixed-signal, and RF design challenges. For more information and/or support, visit LT3502 1.1 MHz, 500 mA Step-Down Regulator www.analog.com/CN0506. 2 LTC4316 Single I C/SMBus Address Translator 10 Mbps/100 Mbps/1000 Mbps Dual Channel, Low Power Industrial Ethernet PHY The circuit consists of two indivudual, independent 10 Mbps, EVALUATION AND DESIGN SUPPORT 100 Mbps, and 1000 Mbps PHYs, each with an energy efficient Circuit Evaluation Boards Ethernet (EEE) PHY core with all the associated common analog CN-0506 Circuit Evaluation Board (EVAL-CN0506-FMCZ) circuitry, input and output clock buffering, management Design and Integration Files interface, subsystem registers, media access control (MAC) Schematics, Layout Files, Bill of Materials interface, and control logic. CIRCUIT FUNCTION AND BENEFITS The design is powered from the host field programmable gate The circuit shown in Figure 1 is a dual channel, low latency, low array (FPGA) mezzanine card (FMC) development board, power Ethernet physical layer (PHY) card that supports 10 Mbps, eliminating the need for an external power supply. A software 100 Mbps, and 1000 Mbps speeds for industrial Ethernet programmable clock enables media independent interface (MII), applications using line and ring network topoligies. reduced MII (RMII), and reduced Gigabit MII (RGMII) MAC Dual channels enable line and ring network topologies that are interface modes. RJ45 ports with integrated magnetics keep the commonly used for industrial sensing, control, and distributed solution as compact as possible. control systems. The ADIN1300 Ethernet PHY was extensively The solution supports cable lengths up to 150 meters at gigabit tested for electromagnetic compatibility (EMC) and electrostatic speeds and up to 180 meters at 100 Mbps or 10 Mbps. This discharge (ESD) robustness and supports automatic negotiation solution is typically used in ring or bus topologies. The automatic to enable linking with remote PHY devices at the highest common negotiation feature of the ADIN1300 allows connection with speed advertised. IEEE 1588 time stamping in the PHY reduces other PHY devices at the highest supported speed. timing uncertainty in real-time applications and enhances link loss detection for redundant and real-time applications. Rev. 0 Circuits from the Lab reference designs from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. determining its suitability and applicability for your use and application. Accordingly, in no event shall Tel: 781.329.4700 www.analog.com Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) Fax: 781.461.3113 2020 Analog Devices, Inc. All rights reserved. CN-0506 Circuit Note LT3502 0.9V 3P3V V SW IN AUX 3P3 3P3VAUX 3.3V 3P3V 1.8V TO 3.3V VADJ VDDIO AVDD 3P3 DVDD 0P9 RGMII/ TMII/ MAC/IF RJ45 ADIN1300 MII AUX 3P3 MDC MDIO XTAL I XTAL O VIN OUT+ CLK+ CLK FMC LPC 125MHz SDA OUT PXO SCL MDC MDIO RGMII/ RJ45 MAC/IF ADIN1300 TMII/ MII XTAL I XTAL O AUX 3P3 CLK+ CLK LTC4316 SDA SDAIN SDAOUT SDA PXO SCL SCLIN SCLOUT SCL Figure 1. EVAL-CN0506-FMCZ Simplified Block Diagram (All Connections and Decoupling Not Shown) Rev. 0 Page 2 of 7 20149-001